JPH0642529B2 - Semiconductor integrated circuit device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having two or more types of buffer circuits having different current capacities as its buffer circuits.

[Technical Background of the Invention] In a semiconductor integrated circuit, for example, an N-channel MOS type LSI (large-scale integrated circuit), a signal from outside the LSI is not directly introduced into the LSI, or a signal from inside the LSI is directly introduced into the LSI. Signals are exchanged between the inside of the LSI and the outside of the LSI via an input buffer or an output buffer without being taken out of the LSI. If a buffer as such an interface and a circuit attached to the buffer are called a buffer circuit, a circuit other than the buffer circuit in the LSI can be called an internal logic.

In such an LSI, the buffer circuit normally supplies a large current to the outside, and the voltage fluctuation of the power supply wiring has a large value, which is taken into consideration to prevent the fluctuation from having a large effect on the internal logic. Power is supplied separately to the buffer circuit and the internal logic.

FIG. 1 shows a part of the output buffer section (for example, the current drawing side) in the LSI as described above.
Reference numerals 12 and 12 denote transistors on the current sink side in an output buffer having a normal current capacity, and 13 and 14 denote transistors on the current sink side in an output buffer having a large current capacity.
5 to 18 are inverters for driving these transistors 11 to 14, and 19 to 22 are the transistors 11 to 14 described above.
An output terminal (pad) connected to one end of, a power supply terminal 23 for the low potential side power supply V _SS , a power supply wiring 24 for a buffer,
Numerals 25 to 28 represent the resistance, 29 represents the power supply wiring for the internal logic, and 30 represents the resistance. Here, in order to reduce the voltage drop due to the power supply wiring 24 from the power supply terminal 23 to the output buffer arranged away from the power supply terminal 23, the width of the wiring 24 is made thicker to reduce its resistance, or the resistance of the output buffer transistor is reduced. Designed to increase the dimension. FIG. 2 shows an arrangement example of the output buffer section in the LSI chip 31. The large current capacity transistors 13 and 14 are the normal capacity transistor 1.
It is farther from the power supply terminal 23 than 1 and 12.

[Problems of Background Art] By the way, when a particularly large current capacity is required for the output buffers 32 and 33 for driving a light emitting diode or the like recently, the thickness of the power supply wiring 24 and It is necessary to increase the dimension of the transistors of the output buffers 32 and 32, which becomes a factor of increasing the chip size of the integrated circuit.

[Object of the Invention] The present invention has been made in view of the above circumstances, and provides a semiconductor integrated circuit device capable of minimizing the increase in the chip size accompanying the increase in the current capacity of the buffer.

[Outline of the Invention] That is, in the semiconductor integrated circuit device of the present invention, the large current input buffer transistor is arranged closer to the power supply terminal than the small current input buffer transistor. Therefore, the power supply wiring between the power supply terminal and the large current buffer becomes shorter than the conventional one, and the dimension of the buffer transistor can be reduced by the amount that the voltage fluctuation of the power supply wiring becomes smaller, and the power supply wiring is thinner than the conventional one. Done,
The increase in the chip size accompanying the further increase in the current of the buffer can be minimized.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 shows a circuit connection of a part (for example, a current drawing side) of the output buffer section of the MOS type LSI.
Reference numeral 2 is a buffer transistor on the current drawing side of the output buffer having the normal current capacity, 13 and 14 are buffer transistors on the current drawing side of the output buffer having a larger current capacity than the normal current capacity, and 15 to 18 are these transistors 11 An inverter driving ~ 14, 19
˜20 is an output terminal (pad) connected to one end of the transistors 11 to 14, 23 is a power supply terminal for the low potential side power supply V _SS , and 32 is a buffer between the transistors 11 to 14 and the power supply terminal 23. The power supply wiring, 33 to 36 are the resistances thereof. Reference numeral 37 denotes an internal block, which is connected to the power supply terminal 23 through a power supply wiring 38,
Reference numeral 39 is a resistance component of the power supply wiring 38.

In the circuit shown in FIG. 3, the high current buffer transistors 13 and 14 are the normal current buffer transistors 1.
It is arranged closer to the power supply terminal 23 than the terminals 1 and 12.
That is, for example, as shown in FIG.
0, high current buffer transistors 13 and 14 are arranged around the power supply terminal 23 (for example, on both sides), and normal current buffer transistors 11 and 12 are arranged apart from this.

Therefore, according to the above-mentioned LSI, the power supply terminal 23 of the power supply wiring 32 and the high-current buffer transistor 13,
Since the distance between the buffer transistor 13 and the buffer transistor 14 is shorter than in the conventional case, the voltage drop of the power supply wiring 32 is reduced, and the buffer transistor 13,
14 dimensions can be reduced. Also,
As described above, the high-current buffer transistors 13, 1
Since 4 is arranged near the power supply terminal 23, the voltage drop due to the resistance component of the power supply wiring between them becomes smaller than before, in other words, the width of this power supply wiring can be made narrower than before. . That is, even when the buffer transistors 13, 14 are made to have a particularly large current for driving a light emitting diode or the like, the dimension thereof increases and the power supply wiring between the buffer transistors 13, 14 and the V _SS power supply terminal 23 is increased. It is possible to minimize the increase in width, that is, the increase in LSI chip size.

Although the above embodiment shows the current drawing side of the output buffer section of the LSI, the same applies to the relationship between the current supply side transistor of the output buffer section and the power supply terminal for the high potential side power supply _VDD . In addition, circuit connection and buffer circuit arrangement can be performed in the input buffer section according to the above.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit device of the present invention, by arranging the input buffer and the power supply terminal rationally, it is possible to reduce the chip size accompanying the increase in current of the input buffer. The increase can be minimized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a part of an output buffer section in a conventional semiconductor integrated circuit device, and FIG. 2 is a diagram for explaining a positional relationship on a chip between a buffer shown in FIG. 1 and a power supply terminal,
FIG. 3 is a circuit diagram showing a part of an output buffer section for explaining one embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 4 is a layout of the buffer and power supply terminal of FIG. 3 on a chip. It is a figure for explaining a relation. 11, 12 ... Normal current buffer transistor, 13,
14 ... Large current buffer transistors, 19 to 20 ... Output terminal, 23 ... Current terminal, 32 ... Power supply wiring.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device which supplies power to a buffer circuit and other internal logics through separate power supply wirings and which has two or more types of buffer circuits having different current capacities as the buffer circuit. A semiconductor integrated circuit device, wherein a buffer transistor of an input buffer circuit is arranged closer to a power supply terminal than a buffer transistor of a small current input buffer circuit, and power supply wiring is provided from this power supply terminal to each of the buffer circuits.