JP3436229B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit built-in type semiconductor device having three power supply systems built therein.

[0002]

2. Description of the Related Art In a conventional input / output (I / O) cell of a semiconductor device using three power supply systems, a first power supply terminal (vdd1) is connected to a chip A (25) as shown in FIG.
The first power supply terminal (vdd1) and the second power supply terminal (vdd
2) is connected to a chip B (26) having a level shift circuit. The third power supply terminal means (vdd3) and the first power supply terminal means (vdd1) are connected to the chip C (27) which is the level shift circuit. In order to set the output of the chip A (25) having the first power supply terminal (vdd1) to the voltage of the second power supply terminal (vdd2), the chip B outputs the signal X having the voltage of the first power supply terminal (vdd1). The first power supply terminal (vdd1) and the second power supply terminal (vdd2) are connected to the first stage input circuit, and the second power supply terminal means (v
dd2) is connected to the second stage input circuit. At this time, the voltage of the second power supply terminal (vdd2) is higher than the voltage of the first power supply terminal (vdd1). Chip A
In the case of outputting the signal X from the IC to the outside at the voltage of the second power supply terminal (vdd2), the chip B, which is an IC dedicated to the level shift, is connected as shown in the figure, and the signal X is connected to the first power supply terminal (vdd1). ) Voltage was converted to the voltage of the second power supply terminal (vdd2).

In order to convert the signal X2 of the first power supply terminal means (vdd1) into the voltage of the third power supply terminal means (vdd3), the voltage of the first power supply terminal means (vdd1) is changed to the third voltage. A chip C, which is a dedicated level shift IC for converting the voltage of the power supply terminal means (vdd3), is connected as shown in the figure, and the signal X2 is changed from the voltage of the first power supply terminal (vdd1) to the third power supply terminal means ( It was converted to the voltage of vdd3).

[0004]

However, the problems of the conventional circuit configuration are: (1) An IC for converting the voltage of the first power supply terminal (vdd1) into the voltage of the second power supply terminal (vdd2). (Chip B level shift circuit) is additionally required, resulting in high cost.

(2) An IC (chip C level shift circuit) for converting the voltage of the first power supply terminal (vdd1) into the voltage of the third power supply terminal (vdd3) is additionally required, which increases the cost.

(3) If the number of I / Os is large, the number of ICs (chip B level shift circuit and chip C level shift circuit) for converting the above voltage is inevitably increased, and the printed circuit board must be enlarged. Not, which leads to a further increase in cost.

(4) Since the signal passes through the IC (chip 3 level shift circuit and chip C) for converting the voltage, the speed becomes extremely slow. (About 800 ns) and so on, there were major problems in terms of performance and price.

(5) Further, the power supply lines of Vdd1, Vdd2 and Vdd3 connected to the chips B and C need to be routed in a complicated manner as shown in FIG.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide a high-performance semiconductor device which has a built-in level shift circuit for converting a voltage at a low cost and a high speed. Further, it is to provide a semiconductor device including a level shift circuit without inconveniently causing complicated wiring and an increase in chip area.

[0010]

The semiconductor device of the present invention comprises:
The internal logic, the ground wiring, the first power supply system wiring, and the at least second and third power wirings, which are provided so as to surround the internal logic so as to make one round respectively.
The internal logic is made possible by a plurality of power system wirings including a power system wiring.
A ring-shaped arrangement formed around the outer circumference of the rack.
Line, the ground wiring, the first power supply system wiring and the second power supply system wiring, a first input / output cell section, the ground wiring, the first power supply system wiring, and the third power supply a second input-output cell unit having a system wiring, a semiconductor device having a, a first level shift circuit for level-shifting a signal of the first power supply system to the signal of the second power supply system,
The signal of the first power supply system is provided in a region sandwiched by two adjacent wirings of the ground wiring, the first power supply system wiring, and the second power supply system wiring, and the signal of the first power supply system is supplied to the third power supply system. A second level shift circuit for level shifting to a signal is provided in a region sandwiched by two adjacent wirings of the ground wiring, the first power supply wiring and the third power supply wiring. And

Further, in the above-described semiconductor device, the first input / output cell portion is a first wiring provided outside the ground wiring, the first power system wiring and the second power system wiring. A second device provided in a region sandwiched between the output pad, the ground wiring and the first power system wiring, and level-shifting the signal of the first power system to the signal of the second power system.
Of the level shift circuit, the first power supply system wiring and the second power supply system wiring, and the second power supply system wiring.
Input the level-shifted signal to the power system signal of
A second inverter circuit for outputting an output signal to the output pad, wherein the second input / output cell section is outside the ground wiring, the first power supply system wiring, and the third power supply system wiring. Is provided in a region sandwiched between the second output pad provided on the second power pad and the ground wiring and the first power supply system wiring, and the signal of the first power supply system is leveled to the signal of the third power supply system. A second level shift circuit for shifting is provided in a region surrounded by the first power supply system wiring and the third power supply system wiring, and a signal level-shifted to the signal of the third power supply system is input. And a second inverter circuit for outputting an output signal to the second output pad. In the semiconductor device of the forth, before Symbol second power supply system line and the third power supply system wiring is characterized in that it is electrically insulated.

In the semiconductor device described above, the voltage of the second power supply system is higher than the voltage of the first power supply system, and the voltage of the third power supply system is the voltage of the first power supply system. It is characterized by higher than.

Further, the semiconductor device described above is characterized in that the voltage of the second power supply system is substantially different from the voltage of the third power supply system.

[0014]

The features of the above-described structure of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1, the first power supply terminal (vdd1) (2) and the second power supply terminal (vdd2)
Connect (1) to the chip and also connect the ground terminal (3). And the third power supply terminal means (vdd3) (28) is also connected to the chip. Here, the second power supply terminal means (vdd
2) and the third power supply terminal means (vdd3) are separated from each other as shown in the figure.

In order to convert the signal from the first power supply terminal means (vdd1) to the voltage of the second power supply terminal means (vdd2), the level shift means shown in FIG. The I / O cells (23) are arranged in the column as shown in the figure, and the output of the level shift means is connected to the second power supply terminal (vdd
It is input to the input of the next-stage implanter (first Pch transistor 9, first Nch transistor, 10) that uses 2) as a power source. The output of the in-park means is directly output to the pad.

As a result, there is no need to attach an IC for converting the voltage of the first power supply terminal (vdd1) to the voltage of the second power supply terminal (vdd2) to the outside, and the IC (for converting the voltage is Since the signal can be converted only in the semiconductor device without passing the signal through the chip B level shift circuit), it is about 2 to about 800 ns as compared with the conventional one.
Since it requires a delay of 0 ns, it has the feature that extremely high speed is possible.

Further, in order to convert a signal from the first power supply terminal means (vdd1) to the voltage of the third power supply terminal means (vdd3), the level shift means (12) is similarly operated by the I / O.
Place it at position 29 in the cell. As a result, the voltage of the first power supply terminal (vdd1) is changed to the third power supply terminal means (vd1).
There is no need to attach an IC for converting the voltage of d3) to the outside, and a signal conversion is performed only within the semiconductor device without passing through the IC (chip C level shift circuit) for converting the voltage. Therefore, the delay is about 200 ns, which is about 800 ns as compared with the conventional one, and therefore the speed can be extremely increased.

[0018]

1 is a layout diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the level shift means shown in FIG.

FIG. 4 is a timing chart for explaining the operation of the level shift means of FIG. 2 in an easy-to-understand manner.

A detailed description will be given with reference to FIGS. 1, 2 and 4.

In FIG. 1, the second power supply terminal (vdd
2) is around the outermost periphery of the chip, and the first power supply terminal (vdd1) is inside thereof. The ground terminal (vss) is further inside.

The first power supply terminal (vdd1) is a PAD
It is supplied from (2) and is connected to the logic inside the chip, and the second power supply terminal (vdd2) is also supplied from PAD (1). Ground terminal (vss) is PAD (3)
Connected to the internal logic of the chip.

The third power supply terminal means (vdd3) is connected to the pad 28 and supplies a voltage to the I / O cell having the level shift means.

I / O cells (23) are arranged in the peripheral portion of the chip. Also, the corners of the chip (4,5, 6,
In 7), I / O cell (22) cannot be placed, so
Normally, only the first power supply terminal (vdd1), the second power supply terminal (vdd2) and the ground terminal (vss) which are power supply lines are turned.

Next, in order to explain the contents of the present invention in an easy-to-understand manner, the circuit diagram of the level shift means shown in FIG. 2 will be described first with reference to the timing chart of FIG. Here, the case where the voltage of the first power supply terminal means is converted to the voltage of the second power supply terminal means is dealt with, but this is changed from the voltage of the first power supply terminal means to the voltage of the third power supply terminal means (vdd3). The same mechanism is used when converting.

In the circuit diagram of the level shift means of FIG. 2, there are a first power supply terminal means (vdd1) and a second power supply terminal means, and the first sound source terminal means (vdd1) is used as a power source and the first input is used. The first inverter means (Pch transistor 13, Nch transistor 14) whose terminal (IA) is an input, the first Pch transistor (15) whose second power source terminal (vdd2) is a source terminal, and the first Pch. A drain terminal of the transistor (15) is used as a source terminal, a gate terminal is connected to the first input terminal (IA), a second Pch transistor (16), and a first input terminal is connected to a gate terminal; A source terminal is grounded, and a drain terminal is connected to the drain terminal of the second Pch transistor (16).
a fourth Pch transistor (18) in which the ch transistor (17) uses the second power supply terminal as a source terminal and the drain terminal of the second Pch transistor (16) is connected to the gate terminal; and the fourth Pch transistor. (1
A fifth Pc in which the drain terminal of 8) is used as a source terminal and the gate terminal is connected to the output of the first inverter means.
The drain terminal of the h transistor (19) and the fifth Pch transistor (19) is connected to the drain terminal,
A sixth Nch transistor (20) whose output terminal is connected to a gate terminal and whose source terminal is grounded, and a second Pch transistor (16).
The second Pch transistor (18), whose drain terminal is connected to the gate terminal, receives the drain terminals of the fourth Pch transistor (18) and the fifth Pch transistor (19) and uses the second power supply terminal (vdd2) as a power source. Inverter means (Pch transistor 21, Nch transistor 22)
It has the configuration of. Although the circuit diagram of the level shift means of FIG. 2 is shown as an example of the configuration of the level shift means in FIG. 1, the way of configuring the level shift means is not limited to this embodiment but this example. Is an example.

Next, the description will be continued with reference to the timing chart of FIG. In FIG. 4, IA is a power supply system signal of the first power supply terminal (vdd1). This signal is supplied to the second power supply terminal (vdd2) by using the level shift means.
Consider the case where IA changes from L to H in the case of converting into a power supply system signal. When IA changes from L to H, which is the power supply system of the first power supply terminal (vdd1), the sixth Nch transistor (20) is turned on, so that the signal e
Goes from H of the power supply system of the second power supply terminal means to L, whereby the output X becomes H of the voltage system of the second power supply terminal means. Accordingly, the first Pch transistor (1
5) is also turned on, and the second Pch transistor (1
6) is ON, the third Nch transistor (17) is OF
Since it becomes F, the signal f becomes H of the voltage system of the second power supply terminal means.
Then, the fourth Pch transistor (18) is turned off. In this way, the voltage system signal of the first power supply terminal means (vdd1) is converted into the voltage system signal of the second power supply terminal means. This conversion takes about 20 ns
However, if this conversion is performed by another IC attached, the time for driving the output part and the load capacitance outside the chip, the time for the input part of the IC of the level shift means, and the time required for the conversion. And the time required for output is about 800
Since it takes ns time, putting the level shift means in the semiconductor has a great effect in terms of performance. Further, since the level shift means is used in the I / O cell portion, the level shift means is provided in the I / O peripheral portion of the semiconductor device.
By putting in the cell, the conversion can be done at high speed.

[0028]

As described above, according to the above configuration of the present invention, the first power supply terminal (vdd1) (2) and the second power supply terminal (vdd2) (1) are connected to the chip, and Connect the ground terminal (3). Third power supply terminal means (vdd
3) is also connected to supply voltage to the I / O cell having the level shift means, and the level shift means shown in FIG. 2 is connected to the I / O cell (2) in the peripheral portion of the chip in FIG.
3) Arranged in the column as shown in the figure, and the output of the level shift means uses the second power supply terminal (vdd2) as a power source for the next-stage inverter (first Pch transistor 9, first Nch).
Input to the transistor, 10). Further, the level shift means connected to the third power supply terminal means (vdd3) is arranged in the I / O cell (29) column in the peripheral portion of the chip in FIG. 1 as shown in the figure to output the level shift means. To the input of the next-stage inverter (first Pch transistor 9, first Nch transistor, 10) which uses the third power supply terminal means (vdd3) as a power supply.

By directly outputting the output of the inverter means to the pad, it is not necessary to attach an IC for converting the voltage of the first power supply terminal (vdd1) to the voltage of the second power supply terminal (vdd2) to the outside. In addition, since the signal can be converted only within the semiconductor device without passing through a signal-transmission IC for converting the voltage, a delay of about 20 ns is required as compared with the conventional one, which is about 20 ns. Extremely high speed is possible. Furthermore, since the power supply wiring to the level shift circuit can be directly made from the Vdd1, Vdd2 and Vss wiring already provided inside the I / O cell, the wiring is complicated and the chip area is increased. There is no invitation. Further, these effects are obtained by changing the voltage of the first power supply terminal means-to the third power supply terminal means (vd
The same can be said when converting to the voltage of d3). In addition, it has a feature that the cost of reducing the need for a chip is eliminated, and the effect is enormous.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a level shift means used in one embodiment of the present invention.

FIG. 3 is a diagram showing an example of a conventional circuit diagram.

FIG. 4 is a timing chart showing the operation of FIG.

[Explanation of symbols]

1 ... PAD of second power supply terminal (vdd2) 2 ... PAD of first power supply terminal (vdd1) 3 ... PAD of ground terminal (vss) 4, 5, 6, 7 ... Corner portion 8 of semiconductor device ... Level shift Means 9 ... Pch transistor 10 ... Nch transistor 11 ... Output pad 12 ... Logic part 13, 21 ... P-type MOS transistor 14, 22 ... N-type MOS transistor 15 ... First Pch transistor 16 ... Second Pch transistor (16) 17 ... Third Pch transistor (17) 18 ... Fourth Pch transistor (18) 19 ... Fifth Pch transistor (19) 20 ... Sixth Pch transistor (20) 23 ... I / O cell section 25 ... Chip A 26 ... Chip B 27 ... Chip C 28 ... Third power supply terminal means (vdd3) 29 ... Third power supply terminal means (vdd) I / O cell having a) system level shifting means

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References Japanese Unexamined Patent Publication No. 1-255317 (JP, A)                 JP-A-2-89345 (JP, A)                 JP-A-1-93145 (JP, A)                 JP-A-1-196917 (JP, A)                 JP-A-2-84815 (JP, A)                 JP 63-168896 (JP, A)                 JP 54-23340 (JP, A)                 JP-A-63-152220 (JP, A)

Claims (5)

(57) [Claims] 1. An internal logic, and a ground wiring, a first power supply system wiring , and at least a second and a third power supply system wiring, which are provided so as to surround the outer peripheral portion of the internal logic so as to make one round respectively. Multiple power supplies
The system wiring will go around the outer peripheral portion of the internal logic.
A first input / output cell portion having a substantially ring-shaped wiring formed as described above, the ground wiring, the first power supply system wiring and the second power supply system wiring, the ground wiring, the first power supply system and wiring and the second input-output cell unit having a third power supply system line, a semiconductor device having a first level shift the signal of the first power supply system to the signal of the second power supply system 1 level shift circuit is provided in a region sandwiched by two adjacent wirings of the ground wiring, the first power supply system wiring and the second power supply system wiring, and a signal of the first power supply system is provided. A second level shift circuit for level-shifting to the signal of the third power supply system is sandwiched between two adjacent wirings among the ground wiring, the first power supply wiring and the third power supply wiring. A semiconductor device provided in a region. 2. The semiconductor device according to claim 1, wherein the first input / output cell section is provided outside the ground wiring, the first power supply system wiring, and the second power supply system wiring. A first output pad; the first level shift circuit provided in a region sandwiched by the ground wiring and the first power system wiring; the first power system wiring and the second power system provided in a region surrounded by lines as input the second signal to the level-shifted signal of the power supply system having a first inverter circuit for outputting an output signal to said output pad, wherein the first The second input / output cell unit includes a second output pad provided outside the ground wiring, the first power system wiring and the third power system wiring, the ground wiring and the first power system. the second level shift provided in a region between the wiring A circuit, provided in a region surrounded by the first power supply system wiring and the third power supply system wiring, having a signal level-shifted to the signal of the third power supply system as an input, and an output signal being the output signal; wherein a has a second inverter circuit for outputting to the second output pad, a. The semiconductor device according to 3. The method of claim 2, before Symbol semiconductor device in which the second power supply system line and said third power supply system wiring is characterized in that it is electrically insulated. 4. The semiconductor device according to claim 2 or 3, wherein the second voltage of the power supply system is higher than the voltage of the first power supply system, the third voltage power supply system is the first The semiconductor device is characterized by having a voltage higher than that of the power supply system of. 5. The semiconductor device according to claim 4,
The semiconductor device, wherein the voltage of the second power supply system has a value that is substantially different from the voltage of the third power supply system.