JP2001144600A - Input/output buffer for semiconductor integrated circuit compatible with multi-power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an input output buffer for semiconductor integrated circuit compatible with multi-power supply that can eliminate a wrong signal output at application of power. SOLUTION: The input output buffer consists of a 1st level shifter and a 2nd level shifter, which have a reset system circuit in the inside to reset an output of each level shifter, and of a tire-state buffer. An output signal of the 1st level shifter is given to an input terminal of the tri-state buffer and an output signal from the 2nd level shifter is given to an output control terminal of the tri-state buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output buffer for an integrated circuit compatible with multiple power supplies, which eliminates erroneous signal output when power is turned on.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor integrated circuits,
The voltage of the power supply has been reduced. However, a semiconductor element having an old-generation high-voltage interface is often mounted on a semiconductor mounting board for the purpose of reducing component costs. To communicate with them, the outside of the semiconductor device is provided with a high-voltage interface designed to withstand high voltages, while the inside is designed to have low voltage and high integration, thereby achieving low power consumption and high speed. The number of multi-power semiconductor integrated circuits having large-scale circuits has increased.

[0003]

However, in a multi-power semiconductor integrated circuit, unexpected operation may occur depending on the power-on sequence. In order to reduce the cost, in a circuit that is used as a control device and directly connects a controlled device, a problem may occur due to an erroneous signal, and a circuit that externally prevents this erroneous operation has conventionally been required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems and circumstances, and overcomes the above-described problems internally, thereby eliminating the need for an external circuit for preventing malfunction.

[0005]

That is, the input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to the present invention can achieve the above object by having the following features. 1. An input / output buffer for a semiconductor integrated circuit for multiple power supplies having a level shifter for converting a signal voltage level,
An input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies, wherein a reset-related circuit for resetting the output of the level shifter is provided to eliminate erroneous signal output at power-on. 2. What is claimed is: 1. An input / output buffer for a multi-power supply semiconductor integrated circuit having a level shifter comprising a signal system circuit and a reset system circuit, wherein said signal system circuit converts an internal signal (101) to a first power supply voltage supplied by a high power supply voltage. Voltage conversion circuit (203
a) is connected to the gate of the first N-type transistor (2032a) and to the first inverter (208) supplied with the low power supply voltage, and the output of the first inverter (208) is connected to the first inverter (208). To the gate of the second N-type transistor (2034a) in the first voltage conversion circuit (203a), and to the first P-type transistor of the first voltage conversion circuit (203a).
The gate and the drain of the type transistor (2031a) and the second P-type transistor (2033a) are connected in a crossover manner, and an output signal (205) of the first voltage conversion circuit is provided.
A second inverter (206) supplied with a high power supply voltage
And the output of the second inverter (206) is connected to the third inverter (207) supplied with the high power supply voltage, and the output of the third inverter (207) is connected to the level shifter output signal (102). ), The reset system circuit (202) has a built-in second voltage conversion circuit (203b) supplied with a high power supply voltage, and the gate of the third N-type transistor (2032b) has a ground potential. And connect
The gate of the fourth N-type transistor (2034b) has
A low power supply voltage is connected, and a third power supply voltage in the second voltage conversion circuit is
The gate and the drain of the P-type transistor (2031b) and the fourth P-type transistor (2033b) are connected in a crossover manner, and the output signal (212) of the second voltage conversion circuit (203b) is connected to the high power supply voltage. Is connected to the fourth inverter (213) supplied with the fourth inverter (213).
The output signal (216) of (3) is connected to the fifth inverter (214) supplied with the high power supply voltage, and the fifth P-type transistor (211) supplied with the high power supply voltage.
Of the fifth P-type transistor (21
The drain of (1) is connected to the output signal (212) of the voltage conversion circuit, and the output signal (215) of the reset circuit, which is the output of the fifth inverter (214), is output to the signal circuit (201). Fifth N-type transistor (204)
Of the fifth N-type transistor (20
4) An input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies, wherein the drain of 4) is connected to the output signal (205) of the first voltage conversion circuit. 3. 3. The multi-layer circuit according to claim 2, wherein a pull-up capacity of the fifth P-type transistor in a conductive state is smaller than a pull-down capacity of the fourth N-type transistor in a conductive state. 4. Input / output buffer for power supply-compatible semiconductor integrated circuits. 4. A first level shifter having the reset circuit therein; a second level shifter having the reset circuit therein; and a tri-state buffer. 2. The output terminal of the tri-state buffer connected to an input terminal, and an output signal of the second level shifter is connected to an output control terminal of the tri-state buffer.
4. The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to any one of 3. 5. 4. The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to claim 1, further comprising a plurality of level shifters sharing the reset circuit with a plurality of signal circuits. 6. A plurality of first signal-related circuits and a plurality of second signal-related circuits, wherein the first signal-related circuit includes a plurality of reset-related circuits, a plurality of output control signals, a plurality of tri-state buffers, and a plurality of external output terminals; 6. The output signal of the tri-state buffer is connected to the input terminal of the tri-state buffer, and the output signal of the second signal-system circuit is connected to the output control terminal of the tri-state buffer. 2. An input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to item 1. 7. The high power supply voltage is approximately 5 V, and the low power supply voltage is approximately 3 V
7. The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to claim 1, wherein: 8. 8. The multi-power-supply semiconductor according to claim 1, wherein the high power supply voltage is a power supply voltage of an external interface of the semiconductor integrated circuit, and the low power supply voltage is an internal power supply voltage of the semiconductor integrated circuit. Input / output buffer for integrated circuits.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An input / output buffer for an integrated circuit compatible with multiple power supplies according to the present invention will be described below in detail with reference to the drawings by way of specific embodiments. FIG. 1 is a circuit diagram of an output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to the first embodiment. FIG.
FIG. 3 is a circuit diagram of a level shifter in an input / output buffer for a semiconductor integrated circuit supporting multiple power supplies according to the present invention. FIG. 3 is a circuit diagram of a plurality of multi-power-supply semiconductor integrated circuit output buffers according to the second embodiment. FIG. 4 is a circuit diagram of a level shifter in a conventional input / output buffer for a semiconductor integrated circuit supporting multiple power supplies. In each drawing, P indicates a P-type MOS transistor, and N indicates an N-type MOS transistor.

(Embodiment 1) In this embodiment, a high power supply voltage VD
D5 (external interface voltage) is 5V, low power supply voltage V
This is an example in which DD3 (internal voltage) is set to 3 V and used for an integrated circuit with two power supplies. In the present embodiment, an output buffer will be described, but the same configuration can be realized for an input buffer.

As shown in FIG. 1, the output buffer 10
It comprises a (first) level shifter 20a, a (second) level shifter 20b, and a tristate buffer 103. The internal signal 101 of 3V is supplied to the level shifter 20a.
, And outputs a level shifter output signal 102. The level shifter output signal 102 outputs a signal to the external output terminal 104 through the tri-state buffer 103. The output control signal 105 is the level shifter 2
After the voltage conversion at 0b, the output of the external output terminal 104 is controlled as the output control signal 106 of the tristate buffer 103.

FIG. 2 is a circuit diagram of the level shifter 20 used in this embodiment. The level shifter 20a and the level shifter 20b have the same circuit configuration. The level shifter 20 includes a signal system circuit 201 and a reset system circuit 202, and is constituted by a MOS transistor. The internal signal 101 of 3 V supplies the high power supply voltage VDD5 (first
To the gate of the (first) N-type transistor 2032a of the voltage conversion circuit 203a).

Further, the internal signal 101 is connected to the (first) inverter 208, and its output is input to the gate of the (second) N-type transistor 2034a. The (first) P-type transistor 20 of the (first) voltage conversion circuit 203a
31a and the (second) P-type transistor 2033a have their gates and drains connected in a crossover manner, and the (first) N-type transistor 2032a and the (second) N-type transistor
It operates together with 034a to convert the power supply voltage. (First
5) The output signal 205 of 5V of the voltage conversion circuit 203a is received by the (second) inverter 206, and its output is further inverted by the (third) inverter 207 to output the level shifter output signal 102.

The reset circuit 202 includes a voltage conversion circuit 2
03 (a), the ground potential GND (0V) is input to the gate of the (third) N-type transistor 2032b, and the gate of the (third) N-type transistor 2032b is The gate has a low power supply voltage VD
Enter D3. Output signal 21 of voltage conversion circuit 203b
2 is received by the (fourth) inverter 213 and the signal 216
Is output.

The output signal 216 of the inverter 213 is transmitted to the (fifth) inverter 214 and the (fifth) inverter 214.
Connected to the gate of the P-type transistor 211, the output of the P-type transistor 211 is fed back to the output signal 212 of the voltage conversion circuit. The output signal 215 of the reset circuit generated by the inverter 214 is input to the gate of the (fifth) N-type transistor 204 of the signal circuit 201, and the output is connected to the output signal 205 of the voltage conversion circuit.

However, the (fifth) P-type transistor 21
The pull-up capacity in the conductive state of 1 is smaller than the pull-down capacity in the conductive state of the N-type transistor 2034b. Further, the N-type transistor 211 is provided to output the output signal 215 of the reset circuit to the signal circuit 201 earlier and to suppress an increase in the voltage of the output signal 205 of the voltage conversion circuit. The level shifter 20b
The internal signal 101 and the level shifter output signal 102 in FIG.

(Operation of Embodiment 1) The operation of the level shifter in this embodiment will be described with reference to FIG. First, a description will be given assuming a steady state in which the power supply voltage is VDD5 = 5V and VDD3 = 3V. The internal signal 101 is set to 3V. The N-type transistor 2032a turns ON, and the P-type transistor 203
3a is turned on, VDD5 is supplied to the output signal 205 of the voltage conversion circuit, and the output signal 205 becomes 5V. At the same time, inverter 2
The 3V internal signal 101 inverted at 08 turns off the N-type transistor 2034a, disconnects the output signal 205 of the voltage conversion circuit from GND, and assists in setting the output signal 205 of the voltage conversion circuit to 5V.

When the N-type transistor 204 is turned off, the output signal 205 of the voltage conversion circuit is held, passes through the inverters 206 and 207, and outputs 5 V to the level shifter output signal 102. Conversely, if 0 V is input to the 3 V internal signal 101, the inverter 208
Is inverted by the N-type transistor 20
The signal is input to 34a and turned on. Output signal 2 of voltage conversion circuit
05 becomes 0V and the P-type transistor 2031a is ON
When the P-type transistor 2033a is turned off, the output signal 205 of the voltage conversion circuit is stabilized at 0V, and 0V is output to the level shifter output signal 102 that has passed through the inverters 206 and 207. At this time, 0 V is input to the N-type transistor 2032a and the N-type transistor 2032a is turned off.

Next, the operation of the reset circuit will be described.
VDD3 is input to the N-type transistor 2034b and turned on, the output signal 212 of the voltage conversion circuit becomes 0V,
By turning on the P-type transistor 2031b and turning off the P-type transistor 2033b, the output signal 212 of the voltage conversion circuit is stabilized at 0V. N-type transistor 2
In 032b, GND (0V) is input and it is OFF. 0V of the output signal 212 of the voltage conversion circuit passes through the inverters 213 and 214, and the output signal 2 of the reset system circuit is output.
As 15, 0 V is supplied to the N-type transistor 204.
The N-type transistor 204 is turned off, and does not affect the output signal 205 of the voltage conversion circuit. Also, the output signal 2 of the inverter 213 that inverts the output signal 212 of the voltage conversion circuit
16 supplies 5 V to the P-type transistor 211 and does not affect the output signal 212 of the voltage conversion circuit.

Next, a description will be given of the operation at the time of turning on the power supply, in which the circuit of this embodiment becomes effective. Usually, in a multi-power circuit board, a low voltage is generated from a high voltage, so that a high voltage VDD5 =
A state where 5V and VDD3 = 0V will be described. First,
The reset circuit 202 will be described first. VDD3 is connected to the gate of the N-type transistor 2034b.
Since VDD3 = 0V, the N-type transistor 2034b is
It is FF. Also, the N-type transistor 2032b
Is connected to GND, and the N-type transistor 2032b is also OFF.

The output signal 212 of the voltage conversion circuit is likely to be 0 V when the power is turned on.
b turns on and supplies VDD5. During this time, the P-type transistor 2033b is also turned on, and the output signal 21 of the voltage conversion circuit is output.
2 to VDD5. P-type transistor 2031b
And 2033b increase the potential of the output signal 212 of the voltage conversion circuit until they are turned off. Next-stage inverter 213
Outputs 0 V to a signal 216 which is an inverted signal of the output signal 212 of the voltage conversion circuit, and the P-type transistor 211 is turned on.
By doing so, the output signal 212 of the voltage conversion circuit is determined at 5V. The output signal 212 of the voltage conversion circuit passes through the inverters 213 and 214, and the output signal
15 becomes 5V.

The signal system circuit 201 at this time will be described. V
Since DD3 = 0V, the internal signal 101 is 0V, and the power supplied to the inverter 208 is also 0V, so that 0V is input to both the gates of the N-type transistor 2032a and the N-type transistor 2034a. This is the same condition as the above-described voltage conversion circuit 203b of the reset system circuit at the time of power-on. The output signal 205 of the voltage conversion circuit is supplied with electric charge from the P-type transistor 2031 and the P-type transistor 2033a, and the voltage will increase. And However, the output signal 215 of the reset circuit 202 is 5 V, which is input to the N-type transistor 204, lowers the level of the output signal 205 of the voltage conversion circuit, passes through the inverters 206 and 207, and detects an error from the level shifter output signal 102. Blocks 5V signal output and outputs 0V.

The level shifters 20a and 20 according to the present embodiment
The operation of FIG. 1 including b will be described. The expected operation of the circuit shown in FIG. 1 is as follows. When the power supply is in a steady state of VDD5 = 5V and VDD3 = 3V, when the output control signal 105 is 3V, and when the internal signal 101 = 3V, the external output terminal 104 outputs 5V. When the signal 101 = 0V, the external output terminal 104
It is expected to output 0V from. At power on,
Even when VDD5 = 5V and VDD3 = 0V, the output control signal 105 = 0V is converted to the signal 106 = 0V by using the level shifter of this embodiment, and the tri-state buffer 103 cuts off the internal signal 101. However, no erroneous signal is output to the external output terminal 104.

If a conventional level shifter is used here, the level shifter output signal 102 and the signal 106 become 5V, the tristate buffer 103 becomes conductive, and 5V is output from the external output terminal 104. FIG. 4 shows a conventional level shifter. When power is turned on, VDD5 = 5
When V and VDD3 = 0V, the N-type transistor 403
2 and 4034 are turned off, the voltage of the signal 405 rises, and an erroneous signal is generated.

In this embodiment, it is possible to prevent an erroneous signal from being output irrespective of the order in which a plurality of power supplies are turned on. Also,
When a plurality of power supplies are generated, there is no need to supply power from the low voltage side, so that restrictions on the power supply device can be reduced, and the number of components on the semiconductor mounting substrate and the cost can be reduced. Further, by using the same circuit for the voltage conversion circuit 203a of the signal system circuit 201 and the voltage conversion circuit 203b of the reset system circuit 202, errors in semiconductor manufacturing are complemented, so that manufacturing conditions are not restricted.

(Embodiment 2) FIG. 3 shows Embodiment 2 according to the present invention.
This will be described with reference to FIG. FIG. 3 is a diagram illustrating a plurality of output buffers in which a signal system circuit of a level shifter is arranged for each signal and a reset system circuit is shared. In this embodiment, as shown in FIG. 3, the signal system circuits 201a,
01b, 201c, 201d, one level shifter reset circuit 202, and 3V internal signals 301, 30
It comprises output control signals 302 and 304 of 2, 3 V, two tri-state buffers 309 and 310, and two external output terminals 311 and 312. The internal signal 301 is connected to the (first) signal system circuit 201a, the output signal 305 is connected to the input of the tristate buffer 309, the output control signal 302 is connected to the (second) signal system circuit 201b, The output becomes the output control signal 306 of the tri-state buffer 309, and the output of the tri-state buffer 309 becomes the external output terminal 31.
1 connected. Similarly, the internal signal 303 is (first
) Is connected to the signal system circuit 201c, and the output signal 30
7 is connected to the input of the tri-state buffer 310,
The output control signal 304 is the (second) signal system circuit 2
01d, its output becomes the output control signal 308 of the tri-state buffer 310, and the output of the tri-state buffer 310 is connected to the external output terminal 312. Output signal 215 of reset circuit 202
Are the signal circuits 201a, 201b, 201c, 201
d is connected to the gate of the N-type transistor 204 inside each (see FIG. 2). Note that the signal system circuit 201
a, 201b, 201c, 201d and reset circuit 2
02 has the same configuration as the signal circuit 201 and the reset circuit 202 described with reference to FIG.

(Operation of Embodiment 2) The signal system circuit 201a,
201b, 201c, 201d201 and the reset circuit 202 operate in the same manner as in the first embodiment. After turning on the power,
3V in the steady state of VDD5 = 5V, VDD3 = 3V
Internal signals 301 and 303, and 3V output control signals 302 and 304 are converted into 5V signals 305 and 307 and 5V output control signals 306 and 308 by the signal system circuit 201 of four level shifters. These 5
The V signal and the output control signal are supplied to the external output terminals 311 and 31 by the tri-state buffers 309 and 310, respectively.
2 to output a 5V signal.

When power is turned on, VDD5 = 5V, VDD3 =
In the state of 0 V, the reset system circuit 202 of the level shifter functions so as to prevent the output of an erroneous signal according to the present invention. When the output signal 215 of the reset system circuit becomes 5 V, an erroneous signal is output from the signal system circuit 201 of the level shifter. Prevent output. The output signal 215 of the reset circuit is connected to the plurality of signal circuits 201, thereby saving the circuit. In this embodiment, the circuit can be saved by sharing the reset system circuit of the level shifter as described above.

[0026]

The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies of the present invention described in detail above has the following effects. 1. It is possible to prevent an erroneous signal from being output irrespective of the order of turning on a plurality of power supplies. 2. When a plurality of power supplies are generated, there is no need to supply power from the low voltage side, so that restrictions on the power supply device can be reduced, and the number of components on the semiconductor mounting substrate and the cost can be reduced. 3. By using the same circuit for the voltage conversion circuit of the signal system circuit and the voltage conversion circuit of the reset system circuit, an error in semiconductor manufacturing is supplemented, so that manufacturing conditions are not restricted.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to a first embodiment.

FIG. 2 is a circuit diagram of a level shifter in an input / output buffer for a semiconductor integrated circuit supporting multiple power supplies according to the present invention.

FIG. 3 is a circuit diagram of a semiconductor integrated circuit output buffer for a plurality of multiple power supplies according to a second embodiment.

FIG. 4 is a circuit diagram of a conventional level shifter in an input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies.

[Explanation of symbols]

VDD5 High power supply voltage (external interface voltage) VDD3 Low power supply voltage (internal voltage) P P-type MOS transistor N N-type MOS transistor 10 Output buffer 20, 20a, 20b: Level shifter 101 Internal signal 102 Level shifter output signal 103 Tri-state buffer 104 External Output terminal 105, 106 Output control signal 201, 201a, 201b, 201c, 201d Signal system circuit 202 Reset system circuit 203a, 203b Voltage conversion circuit 2031a, 2031b, 2033a, 2033b P
Type transistors 2032a, 2032b, 2034a, 2034b N
Type transistor 204 N-type transistor 205 Output signal of voltage conversion circuit 206, 207, 208, 213, 214 Inverter 211 P-type transistor 212 Output signal of voltage conversion circuit 215 Output signal of reset system circuit 216 Output signal of inverter 213 30 Example 2 Multiple output buffers 301, 303 Internal signal 302, 304 3V output control signal 305, 307 Level shifter output signal 306, 3085V output control signal 309, 310 Tri-state buffer 311, 312 External output terminal

Claims (8)

[Claims] 1. An input / output buffer for a multi-power supply semiconductor integrated circuit having a level shifter for converting a signal voltage level, wherein a reset-related circuit for resetting an output of the level shifter is provided, whereby an erroneous signal at power-on is provided. An input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies, characterized by eliminating output. 2. An input / output buffer for a multi-power supply semiconductor integrated circuit having a level shifter including a signal system circuit and a reset system circuit, wherein the signal system circuit supplies an internal signal (101) to a high power supply voltage. The first N-type transistor (2032) in the first voltage conversion circuit (203a)
a) and connected to the first inverter (208) supplied with the low power supply voltage, and outputs the output of the first inverter (208) to the first voltage conversion circuit (20).
3a) is inputted to the gate of the second N-type transistor (2034a), and the first P-type transistor (2031a) and the second P-type transistor (2033a) of the first voltage conversion circuit (203a) are inputted. Each of the gates and the drains is connected in a crossover manner, and an output signal (205) of the first voltage conversion circuit is connected to a second inverter (206) supplied with a high power supply voltage, and the second inverter ( 206) to the third inverter (20) supplied with the high power supply voltage.
7), the output of the third inverter (207) being configured as a level shifter output signal (102);
The reset system circuit (202) includes a second voltage conversion circuit (203b) supplied with a high power supply voltage, and a ground potential is connected to a gate of the third N-type transistor (2032b). A low power supply voltage is connected to the gate of the N-type transistor (2034b) of the fourth P-type transistor and the third P-type transistor in the second voltage conversion circuit.
The gate and the drain of each of the P-type transistors (2033b) are connected in a crossover manner, and the second voltage conversion circuit (2
03b) is connected to the fourth inverter (213) supplied with the high power supply voltage, and the output signal (216) of the fourth inverter (213) is supplied with the high power supply voltage. A fifth inverter (214) is connected to a gate of a fifth P-type transistor (211) supplied with a high power supply voltage, and a drain of the fifth P-type transistor (211) is connected to a voltage conversion circuit. And the output signal (2) of the reset-related circuit, which is the output of the fifth inverter (214).
15) is input to the gate of the fifth N-type transistor (204) of the signal circuit (201), and the drain of the fifth N-type transistor (204) is connected to the output signal (205) of the first voltage conversion circuit. ), An input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies. 3. The fifth P-type transistor (211).
3. The input / output buffer according to claim 2, wherein the pull-up capacity in the conductive state of the semiconductor integrated circuit is smaller than the pull-down capacity in the conductive state of the fourth N-type transistor (2034b). . 4. A first circuit having the reset circuit therein.
, A second level shifter having the reset system circuit therein, and a tri-state buffer, and an output signal of the first level shifter is connected to an input terminal of the tri-state buffer, 4. The input / output buffer according to claim 1, wherein an output signal of a level shifter is connected to an output control terminal of said tri-state buffer. 5. The input / output for a multi-power-supply semiconductor integrated circuit according to claim 1, wherein said reset circuit has a plurality of level shifters shared by a plurality of signal circuits. buffer. 6. A reset circuit, a plurality of output control signals, a plurality of tristate buffers, and a plurality of external output terminals, comprising a plurality of first signal circuits and a plurality of second signal circuits. The output signal of the first signal circuit is connected to an input terminal of the tri-state buffer, and the output signal of the second signal circuit is connected to an output control terminal of the tri-state buffer. 6. The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to claim 5. 7. The input / output buffer according to claim 1, wherein said high power supply voltage is approximately 5 V, and said low power supply voltage is approximately 3 V. 8. The semiconductor device according to claim 1, wherein the high power supply voltage is a power supply voltage of an external interface of the semiconductor integrated circuit, and the low power supply voltage is an internal power supply voltage of the semiconductor integrated circuit.
8. The input / output buffer for a semiconductor integrated circuit compatible with multiple power supplies according to any one of claims 7 to 7.