JPH0453266A - Semiconductor device - Google Patents

Abstract

PURPOSE:To dispense with an IC which is provided outside to convert the voltage of a first power supply terminal into the voltage of a second power supply terminal and to enable signals to be converted only through a semiconductor device without passing through the IC required for converting a voltage by a method wherein the output of an inverter is transmitted to a pad as it is. CONSTITUTION:A first power supply terminal VDD1 2 and a second power supply terminal VDD2 1 are connected to a chip 1, and a ground terminal 3 is connected to the chip. A third power supply terminal means VDD3 is also connected, and a voltage is applied from the third power supply terminal VDD3 to an I/O cell where a level shifting means is provided, the level shifting means is disposed in the I/O cell 23 row around the chip, and the output of the level shifting means is inputted into the succeeding-stage inverter (a first P channel transistor 9 and a first N channel transistor 10) which makes the second power supply terminal VDD2 1 serve as a power supply. A level shifting means connected to the third power supply terminal means VDD3 is disposed in an I/O cell 29 row as shown in a figure, the output of the level shirting means is inputted into the succeeding-stage inverter (a first P channel transistor 9 and a first N channel transistor 10) which makes the third power supply terminal means VDD3 serve as a power supply, and the output of the inverter is transmitted to a pad as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application 1] The present invention relates to a master slice type semiconductor device with a built-in level shift circuit that includes three power supply systems and switches logic only by wiring layers.

[Conventional Technique] In the I/O cell of a master slice semiconductor device that uses three conventional power supply systems and switches logic only in the wiring layer, the first power supply terminal (vddl,
) is connected to the depth Δ(25), and the first power supply terminal (v
d, dl, ) and the second power supply terminal (vdd2) are connected to the depth B (26) where the level shift circuit is located.

Further, the second power terminal means (v dd, 3) and the first power terminal means (v dd 1.) are connected to the depth C (27) where the level shift circuit is located. Chip A (2
In order to make the output of 5) the voltage of the second power supply terminal (vdd2), DEP B converts the signal The terminal (vdd2) is connected to the first stage input circuit, and the second power supply terminal means (vdd2) is connected to the second stage input circuit. At this time, the second power supply terminal (vdd2)
It is assumed that the voltage at the first power supply terminal (Vd d ], , ) is higher than the voltage at the first power supply terminal (Vd d ], , ). When outputting the signal The voltage at the power supply terminal (vddl) was converted to the voltage at the second power supply terminal (vdd2).

Further, in order to convert the signal X2 of the first power terminal means (vddl) to the voltage of the third power terminal means (vdd3), the voltage of the first power terminal means (vddl) must be converted to the voltage of the third power terminal means (vdd3), a dedicated level shift IC is connected as shown in the figure, and the signal x2 is transferred from the voltage of the first power terminal (vddl, ) to the third power terminal means (vdd3 ) voltage.

[Problems to be Solved by the Invention] However, problems with the conventional circuit configuration include (i) the voltage of the first power supply terminal (vddl) to the voltage of the second power supply terminal (vdd2);
) A separate IC (chip B level shift circuit) is required to convert the voltage to the voltage of

(2) A separate IC (chip C level shift circuit) is required to convert the voltage at the first power terminal (v dd 1.) to the voltage at the second power terminal (v dd 3), increasing the cost. becomes higher.

(3) When the number of I/Os is large, ICs (chip B level shift circuit and chip C
As the number of level shift circuits (level shift circuits) increases, the size of the printer 1 board must also be increased, which further increases costs.

(3) The speed becomes extremely slow because the signal passes through the IC (chip B level shift circuit J: and depth C) for converting the voltage. (approximately 800 ns), there were major problems in terms of performance and price.

The present invention is intended to solve these problems, and its purpose is to provide a low-cost, high-speed, high-performance semiconductor arithmetic device with a built-in level shift circuit for converting voltage. It is about providing.

[Means to Solve the Problem] In a master slice type semiconductor device that incorporates three power supply systems and switches logic only through wiring layers, (a) first power supply terminal means; ) second power terminal means; (c) third power terminal means; (cl) first inverter means using the first power terminal means as a power source; (e) connected to the first inverter means. a first input terminal; (f) a second P terminal whose source terminal is the second power supply terminal;
(g) a second Pch transistor whose source terminal is the drain terminal of the first Pch transistor, and whose gate terminal is connected to the first input terminal; One input terminal is connected to the gate terminal, the source terminal is grounded, and the drain terminal is connected to the second P
A third N c h transistor connected to the drain terminal of the c h l □ transistor, (i) the second power supply terminal is the source terminal, and the drain terminal of the second 1] c h t transistor is the gate terminal. a fourth Pch transistor connected to (j) said fourth Pch transistor;
a fifth Pch transistor whose drain terminal is a source terminal and whose gate terminal is connected to the output of the first inverter means; (k,) the drain terminal of said fifth Pch transistor is a drain terminal; (i) the drain terminal of the second Pch transistor is connected to the gate terminal; the output of the first inverter means is connected to the gate terminal; the fourth Pc connected to)
1 transistor, (m) second inverter means using the drain terminal of the fifth Pch transistor as a human power source and the second power supply terminal as a power source, (n) the circuit configuration from (d) to (m) above. (0) A second level shift means in which a third power terminal means is connected in place of the second power terminal means in the circuit configurations (d) to (m) above; (p) The semiconductor device is characterized in that at least one of the first level shift means and the second level shift means are provided in each of the ■ and ○ cell portions in the peripheral area.

C Effect] The features of the above configuration of the present invention will be explained below with reference to FIGS. 1 and 2. In FIG. 1, the first power terminal (v
dd+, ) (2) and the second power supply terminal (vdd2) (i)
Connect to the chip and also connect the ground terminal (3). A third power terminal means (vdd3) (28) is also connected to the chip.

Here, the second power terminal means (vdd2) and the third power terminal means (v dd 3 ) are separated from each other as shown in the figure.

To convert the signal from the first power supply terminal means (vddl) to the voltage of the second power supply terminal means (vdd2), the level shift means shown in FIG. /O cells (23) are arranged as shown in the figure, and the output of the level shift means is connected to the second power supply terminal (v d, d
2) is the power source of the next stage inverter (first Pchh
Lanzisk 9, first N c h transistor, /O
) into the input. The output of the impark means is directly output to the pad.

This eliminates the need to connect an external IC to convert the voltage at the first power terminal (v dd ], ) to the voltage at the second power terminal (vdd2), and also eliminates the need to connect an IC to convert the voltage Since the signal can be converted only within the semiconductor device without passing the signal through the IC (Chip B level shift circuit), it takes approximately 800ns compared to the conventional method, approximately 2
What are the features that make it possible to achieve extremely high speeds with a delay of 0 ns?

Further, in order to convert the signal from the first power terminal means (vddl) to the voltage of the third power terminal means (vdd3), level shift means (i2) is similarly placed at position 29 of the I/O cell. . This allows the first power supply terminal (vdd
It is no longer necessary to attach an external IC for converting the voltage of 1) to the voltage of the third power supply terminal means (vdd3), and the signal does not pass through the IC (chip C level shift circuit) that converts the voltage. Since it is possible to convert signals inside the semiconductor device without any noise, it takes approximately 800 ns compared to conventional methods.
Since the day-to-day noise is approximately 20 ns per day, it has the characteristic of being able to achieve extremely high speeds.

(Embodiment) Fig. 1 is a layout diagram of a semiconductor device according to an embodiment of the present invention.Furthermore, Fig. 2 shows a circuit diagram of level shift 1 to means in Fig. 1.

Further, FIG. 4 is a timing chart diagram for explaining the operation of the level shift means of FIG. 2 in an easy-to-understand manner.

A detailed explanation will be given according to FIGS. 1, 2, and 4.

In FIG. 1, the second power terminal (vdd2) is around the outermost circumference of the depth, and the first power terminal (v d d
],, ) are rotating inside it. and the ground terminal (
VSS) is further inside it.

The first power terminal (vddl,) is supplied from PAD (2) and is connected to the logic inside the chip, and the second power terminal (vdd2) is also supplied from P A I) (]). The ground terminal (vss) is connected to PAD (3) and connected to the internal logic of the chip.

Further, the third power supply terminal means (vdd3) is connected to the pad 28, and is connected to the I/O terminal with the level shift means 1 to 3.
It supplies voltage to the O cell.

I/O cells (23) are lined up around the periphery of the chip.

Also, since I/O cells (22) cannot be placed in some of the corners (4, 5, 6, 7) of the chip, the first power terminal (vddl), which is the power line, and the second power terminal Terminal (v
dd2) and the ground terminal (VSS).

Next, in order to explain the contents of the present invention in an easy-to-understand manner, the circuit diagram of the level shift means shown in FIG. 2 will be explained in accordance with the timing diagram shown in FIG. 4. Here, we will deal with the case of converting the voltage of the first power terminal means to the voltage of the second power terminal means, but this is the case where the voltage of the first power terminal means is converted to the voltage of the third power terminal means (vdd3). The same mechanism is used when converting.

Level shift in Figure 2 - In the circuit diagram of the means, there are first power terminal means (vd, dl) and second power terminal means, the first power terminal means (vddl) is used as a power source, a first inverter means (of which the terminal (IA) is an input);
a first Pcl] transistor (i5) whose source terminal is the second power supply terminal (vdd2);
The drain terminal of the first Pchb transistor (i5) is used as the source terminal, and the second Pcht transistor has terminals connected to the first input terminal (IA).
- a third transistor whose first input terminal is connected to the gate terminal, whose source terminal is grounded and whose drain terminal is connected to the drain terminal of the second Pch transistor (i6); Ncl) transistor (
], 7), the second power terminal is the source terminal and the second P
a fourth Pch transistor (i,8), the drain terminal of which is connected to the gate terminal of the ch transistor (i6);
i8) whose drain terminal is the source terminal and whose gate terminal is connected to the output of the first inverter means;
ch transistor (i9) the drain terminal of the fifth P ch transistor (i9) is connected to the drain terminal, the output of the first inverter means is connected to the gate terminal, and the sixth N c.
h transistor (20), the second P c h t
- the fourth P c )] transistor (i6) whose drain terminal is connected to its gate terminal;
8), the drain terminal of the fifth P c l] transistor (i9) is connected to human power, and the second power supply terminal (vdd2)
It has a configuration of a second impark means (Pchl-run raster 21.Nchl-ransistor 22) whose power source is . The circuit diagram of the level shift means in FIG. 2 is shown as an example of the configuration of the level shift means in FIG.
The configuration of the level shift means is not limited to this embodiment, and this example is just one example.

Next, the explanation will be continued according to the timing chart 1 in FIG. In Fig. 4, IA is the second power supply terminal (
This is a power supply system signal for Vddl, ). In the case where this signal is converted into a power supply system signal of the second power supply terminal (vdd2) using a level shift means, let us consider a case where IA changes from H to H. When IA changes from L to H, which is the power supply system of the first power terminal (vddi), the sixth N
cl] Since the transistor (20) is turned on, the signal e is lowered from 14 of the power supply system of the second power supply terminal means, so that the output
become. Accordingly, the first Pc)]1~ransistor (i5) is also turned ON, and the first Pchl-ransistor (i6)! j: ON, the third Nc h t□ transistor (i7) turns OFF, so the signal becomes H in the voltage system of the second power supply terminal means, and the fourth p c h transistor (i8) is turned off. Turn it OFF. In this way, the voltage system signal of the first power supply terminal means (vddl) is converted into the voltage system signal of the second power supply terminal means. The time required for this conversion is approximately 20 ns, but if this conversion is performed using a separate IC, the time required to drive the output part and the load capacitance outside the chip, and the time required to drive the output part and the load capacitance outside the chip, The time required for the human power section, the time required for conversion, and the time required for output is approximately 800 nS, and placing the level shifter P9 in the semiconductor has a great effect in terms of performance. be. In addition, since the above level shift means is used in the I/O cell part,
By putting this into an I/O cell located at the periphery of the semiconductor device, conversion can be made faster.

[Effects of the Invention 1] As described in 2 below, according to the above configuration of the present invention, the first power terminal (vddl) (2) and the second power terminal (vddl)
d, d 2 ) (i,) are connected to the chip, and the ground terminal (3) is also connected. Third power terminal means (vd
d3) is also connected, from which voltage is supplied to the I/O cell with the level shift means, and the level shift means shown in FIG. (23) The output of the level shift means is placed in the column as shown in the figure, and the next stage inverter (first Pchl~Runsistor 9
, the first Nch l transistor, ]0). In addition, the level shift means connected to the third power supply terminal means (vdd3) is connected to the τ/
Place it in the O cell (29) column as shown in the figure, and connect the output of the novel shift means to the third power terminal means (V d d
3) is used as the power source of the next stage inverter (Pc h
input to the first Nch l-ransistor, /O).

By sending the output of the inverter means directly to the pad, there is no need to connect an IC for converting the voltage of the first power supply terminal (vddl) to the voltage of the second power supply terminal (vdd2), and Since the signal can be converted only within the semiconductor device without passing through the external IC for converting the voltage, the conversion time is approximately 8.
Since there is a delay of approximately 20 ns to 00 ns, extremely high speeds are possible. The same thing can also be said when converting the voltage of the first power terminal means to the voltage of the third power terminal means (vdd3). Moreover, it has the advantage of being able to reduce costs by eliminating the need for a separate chip, and its effects are tremendous.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a semiconductor device showing an embodiment of the present invention. FIG. 2 is a circuit diagram of one novel shift means used in one embodiment of the present invention. FIG. 3 is a diagram showing an example of a conventional circuit diagram. FIG. 4 is a timing chart showing the operation of FIG. 2.・AD of second power supply terminal (vdd2) AD of first power supply terminal (v dd 1.) 3...PAD of ground terminal (vss) 4.5.6.7 1 ・ 8 ・ 1 ] l 2 ・13. 14, 16 ・ 17 ・ 18 ・ 25 ・ 27 ・・Corner level shift means of semiconductor device・・Pch transistor・・Nch transistor output pad・・Logic array part J part P type MO5I-transistor type 1 MOS l-ransistorFirst Pch transistor, second Pcl]t-transistor, third Nchl-transistor, fourth Pch transistor, fifth Pch transistor 6 N ch Transistor T/O cell section Chip A Chip B Depth C (] 7) (] 9] 28. ・Third power supply terminal means (v d, d 3)
29...I/O sensor with level shift means of third power supply terminal means (VDD3) [) Above 8 Applicant: Seiko Epson Corporation

Claims (1)

[Claims] In a master slice type semiconductor device that incorporates three power supply systems and switches logic only through wiring layers, (a) a first power supply terminal means; (b) a second power supply system; (c) third power terminal means; (d) first inverter means using the first power terminal means as a power source; (e) a first input terminal connected to the first inverter means. , (f) the first P whose source terminal is the second power supply terminal
ch transistor, (g) a second Pch transistor whose source terminal is the drain terminal of the first Pch transistor, and whose gate terminal is connected to the first input terminal; (h) whose first input terminal is the gate; terminal, the source terminal is grounded, and the drain terminal is connected to the second Pch.
A third N connected to the drain terminal of the transistor
ch transistor, (i) the second power supply terminal is the source terminal, and the second Pch
a fourth Pch transistor in which the drain terminal of the transistor is connected to the gate terminal; (j) the fourth Pch transistor;
(h) a fifth Pch transistor having a drain terminal of the transistor as a source terminal and a gate terminal connected to the output of the first inverter means; (k) a drain terminal of the fifth Pch transistor connected to the drain terminal; a sixth Nch transistor whose gate terminal is connected to the output of the first inverter means and whose source terminal is grounded; (l) said fourth Pch transistor whose drain terminal is connected to the gate terminal of said second Pch transistor; transistor, (m) second inverter means that uses the drain terminal of the fifth Pch transistor as an input and the second power supply terminal as a power source, (n) has the circuit configuration from (d) to (m) above. a first level shift means; (o) a second level shift means in which a third power supply terminal means is connected in place of the second power supply terminal means in the circuit configurations (d) to (m); p) A semiconductor device, wherein at least one of the first level shift means and the second level shift means are provided in an I/O cell portion in a peripheral portion of the semiconductor device.