US20180197850A1 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit device Download PDFInfo
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- US20180197850A1 US20180197850A1 US15/918,659 US201815918659A US2018197850A1 US 20180197850 A1 US20180197850 A1 US 20180197850A1 US 201815918659 A US201815918659 A US 201815918659A US 2018197850 A1 US2018197850 A1 US 2018197850A1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the present invention relates to chip area reduction techniques for semiconductor devices, and more particularly to a technique useful for layout area reduction in the “PAD on I/O (Input/Output)” cell structure.
- pads coupled with bonding wires or the like are overlapped with I/O cells as interfaces with the outside, which is called the “PAD on I/O cell” structure.
- the output buffer block includes, for example, an output buffer comprised of a P-channel MOS transistor and an N-channel MOS transistor, a first and a second diode for ESD (electrostatic discharge) protection, a first and a second resistance, and an ESD protection circuit.
- the first and second diodes for ESD protection are coupled in series between the supply voltage and reference potential.
- One coupling end of the P-channel MOS transistor is coupled with the supply voltage and the other coupling end of the transistor is coupled with one coupling end of the first resistance.
- the other coupling end of the first resistance is coupled with one coupling end of the second resistance and the other coupling end of the second resistance is coupled with one coupling end of the N-channel MOS transistor.
- the other coupling end of the N-channel MOS transistor is coupled with the reference potential.
- the ESD protection circuit is coupled between the supply voltage and reference voltage.
- a pad is coupled with the junction of the first and second diodes and the junction of the first and second resistances.
- the above circuit configuration has the following drawback: a pad is coupled with the junction of the first and second resistances and thus the lead part coupled with the pad is forced to lie between these two resistances, and as a consequence, the pad will protrude from the I/O cell and the chip area cannot be reduced effectively.
- An object of the present invention is to provide a technique that in the “PAD on I/O (Input/Output) cell” structure, the pad lead part is disposed almost in the center of the I/O part (cell) so as to reduce the semiconductor chip layout area.
- a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads.
- the I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block for controlling the output buffer and an input buffer.
- the logic block, the N-channel transistor, and the P-channel transistor are arranged toward an edge of the semiconductor chip in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the N-channel transistor.
- a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
- the output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and P-channel transistor.
- the output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
- a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
- a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads.
- the I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block which includes an input buffer block functioning as an interface for input of signals from the outside and controls the output buffer and the input buffer.
- the logic block, the P-channel transistor, and the N-channel transistor are arranged in line in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the P-channel transistor.
- a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
- the output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and the P-channel transistor.
- the output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
- a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
- the number of constituent elements of the protection circuit of the output buffer block can be decreased.
- FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention
- FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown in FIG. 1 in enlarged form
- FIG. 3 shows an example of the layout of an I/O part on the semiconductor chip shown in FIG. 1 ;
- FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown in FIG. 3 ;
- FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown in FIG. 3 ;
- FIG. 6 shows the position of a pad coupled with the I/O part shown in FIG. 3 ;
- FIG. 7 is a sectional view of the I/O part shown in FIG. 3 ;
- FIG. 8 is a plan view of a transistor provided in the output buffer block shown in FIG. 3 , combined with a sectional view thereof;
- FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined.
- FIG. 10 shows the layout of the output buffer block in the I/O part shown in FIG. 9 ;
- FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout
- FIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment
- FIG. 13 shows an example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 14 shows another example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 15 is a circuit diagram showing an example of the configuration of an output buffer block according to a second embodiment of the present invention.
- FIG. 16 shows an example of the layout of the output buffer block shown in FIG. 15 ;
- FIG. 17 shows an example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 18 shows another example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 19 shows an example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 20 shows another example of the layout of an I/O part according to another embodiment of the invention.
- FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention.
- FIG. 22 shows an example of the layout of the output buffer block shown in FIG. 21 ;
- FIG. 23 shows an example of the layout of an output buffer block according to another embodiment of the invention.
- FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention
- FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown in FIG. 1 in enlarged form
- FIG. 3 shows an example of an I/O part on the semiconductor chip shown in FIG. 1
- FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown in FIG. 3
- FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown in FIG. 3
- FIG. 6 shows the position of a pad coupled with the I/O part in FIG. 3
- FIG. 7 is a sectional view of the I/O part shown in FIG. 3 ;
- FIG. 8 is a plan view of a transistor provided in the output buffer block shown in FIG. 3 , combined with a sectional view thereof;
- FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined;
- FIG. 10 shows the layout of the output buffer block in the I/O part shown in FIG. 9 ;
- FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout; and
- FIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment.
- a semiconductor chip 1 which is provided in a semiconductor integrated circuit device has a plurality of pads 2 arranged in lines in four peripheral areas as shown in FIG. 1 , in which the pads are coupled, for example, with bonding wires.
- a plurality of pads 2 a which also function as I/O pads are arranged in lines, in which the pads 2 and pads 2 a are arranged in two rows and in a staggered pattern.
- an I/O region 3 as an interface with the outside lies under the pads 2 and 2 a , forming a so-called “PAD on I/O” structure.
- a core region 4 Located in the center of the semiconductor chip 1 is a core region 4 in which a logic circuit including semiconductor elements such as transistors is formed.
- FIG. 2 illustrates, in enlarged form, pads 2 and 2 a and part of the I/O region 3 (area indicated by dotted line in FIG. 1 ) in the PAD on I/O structure.
- a plurality of I/O parts 5 are arranged in a row along each edge of the semiconductor chip 1 and pads 2 and 2 a are arranged in two rows above them in a staggered pattern.
- the I/O parts 5 and pads 2 and 2 a are each rectangular and the long edge of each of the pads 1 and 2 a is, for example, approximately half of the long edge of the I/O parts 5 .
- a pad lead part 5 a is formed on one short edge side of each pad 2 (or 2 a ) and the center of the I/O part 5 is coupled with the corresponding pad 2 (or pad 2 a ) through the part lead part 5 a.
- FIG. 3 shows an example of the layout of the I/O part 5 and FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block 7 provided in the I/O part 5 .
- the I/O part 5 includes a logic block 6 and an output buffer block 7 .
- the logic block 6 includes an ESD protection circuit 6 a (shown in FIG. 4 ), an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to the output buffer block 7 .
- the output buffer block 7 includes transistors 8 and 9 for output buffer, diodes 10 and 11 for ESD protection, and a resistance 12 for ESD protection.
- the transistor 8 is a P-channel MOS transistor and the transistor 9 is an N-channel MOS transistor.
- the diodes 10 and 11 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
- One coupling end of the transistor 8 is coupled with the supply voltage VCCQ and the other coupling end of the transistor 8 is coupled with one coupling end of the resistance 12 .
- the other coupling end of the resistance 12 is coupled with one coupling end of the transistor 9 and the other coupling end of the transistor 9 is coupled with the reference potential VSSQ.
- the junction of the diode 10 , a first diode, and the diode 11 , a second diode, and the junction of the other coupling end of the resistance 12 and the one coupling end of the transistor 9 form an output part for the output buffer block 7 which is coupled with a pad 2 (or pad 2 a ).
- the transistor 8 is located nearest to the periphery of the semiconductor chip 1 in the I/O part 5 .
- the resistance 12 lies above the transistor 8 and the diodes 10 and 11 lie above the resistance 12 .
- the transistor 9 lies above the diodes 10 and 11
- the logic block 6 lies above the transistor 9 with the pad lead part 5 a , for example, formed in a metal wiring layer between them.
- FIG. 5 shows the arrangement of go-round power-supply wires formed over the I/O part 5 shown in FIG. 3 .
- the go-round power-supply wires are arranged as follows: go-round wire for core supply voltage 13 , go-round wire for core reference potential 14 , go-round wires for I/O supply voltage 15 , and go-round wires for I/O reference potential 16 are arranged over the logic block 6 ; and go-round wires for I/O reference potential 17 and go-round wires for I/O supply voltage 18 are arranged over the output buffer block 7 , with the pad lead part 5 a between the two groups of go-round wires.
- the go-round wire for core supply voltage 13 feeds the supply voltage to the core region 4 and the go-round wire for core reference potential 14 feeds the reference potential to the core region 4 .
- the go-round wires for I/O supply voltage 15 and 18 feed supply voltage VCCQ to the I/O part 5 and the go-round wires for I/O reference potential 16 and 17 feeds reference potential VSSQ to the I/O part 5 .
- FIG. 6 shows the position of the pad 2 coupled with the I/O part 5 shown in FIG. 5 .
- This pad 2 is one of the pads located on the outer side (the peripheral side of the semiconductor chip 1 ) among the pads 2 arranged in a staggered pattern and the pad 2 is in such a position that it does not protrude from the short edge of the I/O part 5 on the peripheral side of the semiconductor chip 1 .
- FIG. 7 is a sectional view of the I/O part 5 shown in FIG. 3 .
- the logic block 6 and the transistor 9 , diode 11 and diode 10 , resistance 12 and transistor 8 of the output buffer block 7 are formed from left to right in FIG. 7 .
- the go-round wire for core supply voltage 13 In the wiring layer lying over the device formation layer, the go-round wire for core supply voltage 13 , the go-round wire for core reference potential 14 , go-round wires for I/O supply voltage 15 , go-round wires for I/O reference potential 16 , go-round wires for I/O reference potential 17 , and go-round wires for I/O supply voltage 18 are formed from left to right in FIG. 7 .
- the pad lead part 5 a and pad 2 are formed.
- the pad lead part 5 a and pad 2 are so formed that they lie over the output buffer block 7 formed in the device formation layer.
- the transistor 9 (indicated by the dotted line circle in FIG. 4 ) is manufactured in a way that a conductive film is not formed in part of the diffusion layer, in order for the drain of the transistor 9 to have a high resistance.
- FIG. 8 is a plan view of the transistor 9 , combined with a sectional view thereof.
- a P-well 19 is formed over a semiconductor substrate, and an N+ type semiconductor region 20 functioning as a drain and an N+ type semiconductor region 21 functioning as a source are formed on the right and left over the P-well 19 .
- a conductive film which is a metal silicide 22 such as cobalt silicide or nickel silicide.
- a metal silicide 23 is formed over the N+ type semiconductor region 20 as well, though the region 20 is not all covered by the metal silicide 23 unlike the N+ type semiconductor region 21 and the metal silicide 23 is only formed over part of the region 20 which is coupled with a via 25 for coupling with a wire 24 formed in the overlying wiring layer.
- the sheet resistance can be increased, for example, to a level approximately 10 to 50 times higher than when a metal silicide is formed all over the N+ type semiconductor region 20 .
- a gate 26 is formed over the P-well 19 through an insulating film such as silicon oxide.
- the drain terminal can have a high resistance so that the transistor 9 is protected from ESD.
- FIG. 9 is a circuit diagram of an ordinary I/O part 50 which the present inventors have examined.
- the I/O part 50 (shown in FIG. 10 ) includes a logic block 51 ( FIG. 10 ) and an output buffer block 52 .
- the logic block 51 includes an ESD protection circuit, an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to the output buffer block 52 .
- the output buffer block 52 includes transistors 53 and 54 for output buffer, diodes 55 and 56 for ESD protection, and resistances 57 and 58 for ESD protection.
- the transistor 53 is a P-channel MOS transistor and the transistor 54 is an N-channel MOS transistor.
- the diodes 55 and 56 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
- One coupling end of the transistor 53 is coupled with the supply voltage VCCQ and the other coupling end of the transistor 53 is coupled with one coupling end of the resistance 57 .
- the other coupling end of the resistance 57 is coupled with one coupling end of the resistance 58 and the other coupling end of the resistance 58 is coupled with one coupling end of the transistor 54 .
- the other coupling end of the transistor 54 is coupled with the reference potential VSSQ.
- the junction of the diode 55 and diode 56 and the junction of the resistance 53 and resistance 54 are coupled with a pad lead part 59 which forms an output part for the output buffer block 52 .
- FIG. 10 shows the layout of the output buffer block 52 in the I/O part 50 shown in FIG. 9 .
- the logic block 51 lies in an upper part of the figure and the transistor 54 of the output buffer block 52 lies below the logic block 51 .
- the resistance 58 lies below the transistor 54 and the diode 56 lies below the resistance 58 .
- the diode 55 lies below the diode 56 with the pad lead part 59 between them.
- the resistance 57 lies below the diode 55 and the transistor 53 lies below the resistance 57 .
- the pad lead part 59 to be coupled with a pad 60 can only be placed between the resistance 57 and resistance 58 and as a consequence, the pad lead part 59 should be located off the center of the I/O part 50 , resulting in a protrusion from the short edge of the I/O part 50 as shown on the left in FIG. 11 . This leads to a larger semiconductor chip.
- the structure of the transistor 9 shown in FIG. 8 eliminates the need for a resistance equivalent to the resistance 58 and permits the pad 2 (or pad 2 a ) through the drain of the transistor 9 to be on the same node, so the pad lead part 5 a can be disposed almost in the center of the I/O part 5 as shown on the right in FIG. 11 .
- the pads 2 on the outer side (on the peripheral side of the semiconductor chip 1 ) among the pads arranged in a staggered pattern can be moved toward the center of the semiconductor chip 1 and the inner pads 2 a located nearer to the center of the semiconductor chip 1 than the pads 2 can be moved toward the outer peripheral side of the semiconductor chip 1 .
- the pads 2 and 2 a can be located inside the I/O part 5 without the need for decreasing the size of the pads 2 and 2 a.
- the diodes 10 and 11 and the resistance 12 are placed between the transistors 8 and 9 , so the distance between the transistors 8 and 9 can be increased, so latch-up phenomena due to parasitic thyristors (SCR) is prevented and the reliability is improved.
- the protection circuit in the output buffer block 7 can be smaller.
- the pads 2 and 2 a are arranged in an overlaid manner, so as not to protrude from the I/O part 5 , the chip area of the semiconductor chip 1 can be decreased, making it possible to realize a smaller and low-cost semiconductor integrated circuit device.
- transistor 9 diode 11 , diode 10 , resistance 12 and transistor 8 are arranged in order from top to bottom when seen in the plan view of FIG. 3 in the first embodiment, the order of arrangement may be altered.
- the layout of the output buffer block may be altered as follows: the diode 11 , diode 10 , transistor 9 , resistance 12 , and transistor 8 are arranged from top to bottom as shown in FIG. 13 or the diode 10 , transistor 9 , diode 11 , resistance 12 , and transistor 8 are arranged from top to bottom as shown in FIG. 14 .
- FIG. 15 is a circuit diagram showing an example of the configuration of an output buffer block 7 according to a second embodiment of the present invention and FIG. 16 shows an example of the layout of the output buffer block shown in FIG. 15 .
- the semiconductor chip 1 is the same as the one shown in FIG. 1 in the aforementioned embodiment except the structure of the output buffer block 7 provided in the I/O part 5 .
- the output buffer block 7 includes diodes 10 and 11 and transistors 8 a and 9 .
- the diodes 10 and 11 are coupled in series between supply voltage VCCQ and reference potential VSSQ.
- One coupling end of the transistor 8 a a P-channel MOS transistor, is coupled with the supply voltage VCCQ and the other coupling end of the transistor 8 a is coupled with one coupling end of the transistor 9 , an N-channel MOS transistor.
- the other coupling end of the transistor 9 is coupled with the reference potential VSSQ.
- the junction of the diode 10 and diode 11 , and the junction of the transistor 8 a and transistor 9 form an output part for the output buffer block 7 which is coupled with a pad 2 or pad 2 a.
- a metal silicide film is not formed over part of the upper surface of the N+ type semiconductor region which functions as a drain, so that the drain terminal has a high resistance.
- the drain terminal of the transistor 8 a can have the same function as the resistance 12 ( FIG. 4 ), the resistance 12 is no longer needed.
- FIG. 16 illustrates an example of the layout of the I/O part 5 .
- the logic block 6 lies in an upper part of the figure and the transistor 9 lies below the logic block 6 with the pad lead part 5 a between them.
- the diodes 10 and 11 lie below the transistor 9
- the transistor 8 a lies below the diodes.
- the pad lead part 5 a can be located almost in the center of the I/O part 5 , so the chip area of the semiconductor chip 1 ( FIG. 1 ) can be smaller. This also eliminates the need for the resistance 12 ( FIG. 4 ), which means that the circuit of the output buffer block 7 can be even smaller.
- the layout of the output buffer block 7 as shown in FIG. 16 may be varied as follows: for example, as show in FIG. 17 , the diodes 11 and 10 lie between the transistor 8 a and transistor 9 and their positions are reversed or as shown in FIG. 18 , the diodes 10 and 11 lie between the logic block 6 and the transistor 9 with the pad lead part 5 a between them.
- FIG. 19 Another possible layout of the output buffer block 7 is that as shown in FIG. 19 , the pad lead part 5 a lies between the diodes 11 and 10 and the transistor 9 or as shown in FIG. 20 , the pad lead part 5 a lies between the diode 11 and diode 10 .
- FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention and FIG. 22 shows an example of the layout of the output buffer block shown in FIG. 21 .
- the circuit of the output buffer block includes a resistance 27 in addition to the diodes 10 and 11 and transistors 8 a and 9 included in the second embodiment as shown in FIG. 15 .
- One coupling end of the resistance 27 is coupled with the junction of the diodes 10 and 11 and the other coupling end of the resistance 27 is coupled with the junction of the transistor 8 a and transistor 9 .
- the other elements are coupled in the same way as those in the second embodiment as shown in FIG. 15 .
- FIG. 22 illustrates an example of the layout of the I/O part 5 .
- the logic block 6 When seen in the plan view ( FIG. 22 ), in the I/O part 5 , the logic block 6 lies in an upper part of the figure and the diode 10 and diode 11 lie below the logic block 6 with the pad lead part 5 a between the logic block and the diodes.
- the resistance 27 lies below the diode 11 and the transistor 9 lies below the resistance 27 , and the transistor 8 lies below the transistor 9 .
- the pad lead part 5 a can be located almost in the center of the I/O part 5 , so the chip area of the semiconductor chip 1 ( FIG. 1 ) can be smaller.
- the layout of the output buffer block 7 as shown in FIG. 22 may be varied as follows: for example, as shown in FIG. 23 , the positions of the transistor 8 a and transistor 9 are reverse to those shown in FIG. 22 .
- the present invention is suitable as a chip area reduction technique for semiconductor integrated circuit devices with a “PAD on I/O (Input/Output)” cell structure.
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Abstract
A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.
Description
- The disclosure of Japanese Patent Application No. 2008-323589 filed on Dec. 19, 2008 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
- The present invention relates to chip area reduction techniques for semiconductor devices, and more particularly to a technique useful for layout area reduction in the “PAD on I/O (Input/Output)” cell structure.
- In recent years, with the growing demand for low-cost and smaller semiconductor integrated circuit devices, efforts towards cost reduction with smaller semiconductor chip sizes have been made. For smaller chip sizes, it is necessary to reduce the layout area in which components to be packaged are arranged.
- One of the known layout area reduction techniques is that pads coupled with bonding wires or the like are overlapped with I/O cells as interfaces with the outside, which is called the “PAD on I/O cell” structure.
- However, the present inventors have found that the PAD on I/O cell technology has the following problem.
- In an I/O cell, the output buffer block includes, for example, an output buffer comprised of a P-channel MOS transistor and an N-channel MOS transistor, a first and a second diode for ESD (electrostatic discharge) protection, a first and a second resistance, and an ESD protection circuit.
- The first and second diodes for ESD protection are coupled in series between the supply voltage and reference potential. One coupling end of the P-channel MOS transistor is coupled with the supply voltage and the other coupling end of the transistor is coupled with one coupling end of the first resistance.
- The other coupling end of the first resistance is coupled with one coupling end of the second resistance and the other coupling end of the second resistance is coupled with one coupling end of the N-channel MOS transistor.
- The other coupling end of the N-channel MOS transistor is coupled with the reference potential. The ESD protection circuit is coupled between the supply voltage and reference voltage. A pad is coupled with the junction of the first and second diodes and the junction of the first and second resistances.
- Because of restrictions related to bonding with bonding wires, it is difficult to adopt smaller pads, so in order to maximize chip area reduction, it is desirable to maximize the area in which a pad and an I/O cell overlap each other.
- However, the above circuit configuration has the following drawback: a pad is coupled with the junction of the first and second resistances and thus the lead part coupled with the pad is forced to lie between these two resistances, and as a consequence, the pad will protrude from the I/O cell and the chip area cannot be reduced effectively.
- Another problem is the recent tendency that micro fabrication processes have been increasingly used and wire resistances are high and the resistance of wiring to the ESD protection circuit is also high. As a consequence, the discharge characteristics of the ESD protection circuit may deteriorate, which may cause ESD surge to be discharged to the reference potential through the N-channel MOS transistor located remotely from the ESD protection circuit, resulting in damage to the device.
- If the wire resistance is high, one possible approach is to increase the number of ESD protection circuits to protect the device. However, this approach has the problem that the chip area must be larger.
- An object of the present invention is to provide a technique that in the “PAD on I/O (Input/Output) cell” structure, the pad lead part is disposed almost in the center of the I/O part (cell) so as to reduce the semiconductor chip layout area.
- The above and further objects and novel features of the invention will more fully appear from the following detailed description in this specification and the accompanying drawings.
- Preferred embodiments of the invention which will be disclosed herein are briefly outlined below.
- According to one aspect of the present invention, there is provided a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads. The I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block for controlling the output buffer and an input buffer. In the I/O part, the logic block, the N-channel transistor, and the P-channel transistor are arranged toward an edge of the semiconductor chip in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the N-channel transistor.
- In the N-channel transistor, a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
- The output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and P-channel transistor.
- The output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
- Furthermore, in the P-channel transistor, a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
- Other preferred embodiments of the invention are briefly described below.
- According to another aspect of the invention, there is provided a semiconductor integrated circuit device including a semiconductor chip, in which the semiconductor chip includes a plurality of I/O pads disposed along edges of the semiconductor chip, and a plurality of I/O parts disposed on the semiconductor chip and coupled with any of the I/O pads. The I/O parts each include an output buffer block including an N-channel transistor and a P-channel transistor to form an output buffer and functioning as an interface for output of signals to the outside, and a logic block which includes an input buffer block functioning as an interface for input of signals from the outside and controls the output buffer and the input buffer. In the I/O part, the logic block, the P-channel transistor, and the N-channel transistor are arranged in line in order and a pad lead part to be coupled with the I/O pad lies between the logic block and the P-channel transistor.
- In the N-channel transistor, a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the N-channel transistor can have a high resistance.
- The output buffer block may include a first and a second diode for ESD protection and the first and second diodes may lie between the N-channel transistor and the P-channel transistor.
- The output buffer block may have a resistance for ESD protection and the resistance may lie between the first and second diodes and the P-channel transistor.
- Furthermore, in the P-channel transistor, a conductive film may not be formed over part of a main surface of a semiconductor region functioning as a drain, so that a drain terminal of the P-channel transistor can have a high resistance.
- The advantageous effects achieved by the preferred embodiments of the present invention as disclosed herein are briefly summarized as follows:
- (1) The number of constituent elements of the protection circuit of the output buffer block can be decreased.
- (2) The pad area protruding from the I/O part can be considerably reduced so that the chip area of the semiconductor chip can be smaller.
- Due to the effects mentioned above in (1) and (2), it is possible to provide a smaller and low-cost semiconductor integrated circuit device.
-
FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention; -
FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown inFIG. 1 in enlarged form; -
FIG. 3 shows an example of the layout of an I/O part on the semiconductor chip shown inFIG. 1 ; -
FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown inFIG. 3 ; -
FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown inFIG. 3 ; -
FIG. 6 shows the position of a pad coupled with the I/O part shown inFIG. 3 ; -
FIG. 7 is a sectional view of the I/O part shown inFIG. 3 ; -
FIG. 8 is a plan view of a transistor provided in the output buffer block shown inFIG. 3 , combined with a sectional view thereof; -
FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined; -
FIG. 10 shows the layout of the output buffer block in the I/O part shown inFIG. 9 ; -
FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout; -
FIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment; -
FIG. 13 shows an example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 14 shows another example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 15 is a circuit diagram showing an example of the configuration of an output buffer block according to a second embodiment of the present invention; -
FIG. 16 shows an example of the layout of the output buffer block shown inFIG. 15 ; -
FIG. 17 shows an example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 18 shows another example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 19 shows an example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 20 shows another example of the layout of an I/O part according to another embodiment of the invention; -
FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention; -
FIG. 22 shows an example of the layout of the output buffer block shown inFIG. 21 ; and -
FIG. 23 shows an example of the layout of an output buffer block according to another embodiment of the invention. - Next, the preferred embodiments of the present invention will be described in detail referring to the accompanying drawings. In all the drawings that illustrate the preferred embodiments, elements with like functions are designated by like reference numerals and repeated descriptions of such elements are omitted.
-
FIG. 1 illustrates the layout of a semiconductor chip according to a first embodiment of the present invention;FIG. 2 illustrates pads and part of an I/O region on the semiconductor chip shown inFIG. 1 in enlarged form;FIG. 3 shows an example of an I/O part on the semiconductor chip shown inFIG. 1 ;FIG. 4 is a circuit diagram showing an example of the configuration of an output buffer block in the I/O part shown inFIG. 3 ;FIG. 5 shows the arrangement of go-round power-supply wires formed in a wiring layer over the I/O part shown inFIG. 3 ;FIG. 6 shows the position of a pad coupled with the I/O part inFIG. 3 ;FIG. 7 is a sectional view of the I/O part shown inFIG. 3 ;FIG. 8 is a plan view of a transistor provided in the output buffer block shown inFIG. 3 , combined with a sectional view thereof;FIG. 9 is a circuit diagram of an ordinary I/O part which the present inventors have examined;FIG. 10 shows the layout of the output buffer block in the I/O part shown inFIG. 9 ;FIG. 11 shows comparison between the I/O part according to the first embodiment of the invention and the ordinary I/O part examined by the present inventors in terms of layout; andFIG. 12 shows the positional relation between I/O parts and pads according to the first embodiment. - In the first embodiment, a
semiconductor chip 1 which is provided in a semiconductor integrated circuit device has a plurality ofpads 2 arranged in lines in four peripheral areas as shown inFIG. 1 , in which the pads are coupled, for example, with bonding wires. - Inside the
pads 2 which function as I/O pads (or nearer to the center of the semiconductor chip 1), a plurality ofpads 2 a which also function as I/O pads are arranged in lines, in which thepads 2 andpads 2 a are arranged in two rows and in a staggered pattern. - In the
semiconductor chip 1, an I/O region 3 as an interface with the outside lies under thepads semiconductor chip 1 is acore region 4 in which a logic circuit including semiconductor elements such as transistors is formed. -
FIG. 2 illustrates, in enlarged form,pads FIG. 1 ) in the PAD on I/O structure. - In the I/
O region 3, a plurality of I/O parts 5 are arranged in a row along each edge of thesemiconductor chip 1 andpads O parts 5 andpads pads O parts 5. - A pad
lead part 5 a is formed on one short edge side of each pad 2 (or 2 a) and the center of the I/O part 5 is coupled with the corresponding pad 2 (orpad 2 a) through thepart lead part 5 a. -
FIG. 3 shows an example of the layout of the I/O part 5 andFIG. 4 is a circuit diagram showing an example of the configuration of anoutput buffer block 7 provided in the I/O part 5. - As shown in
FIG. 3 , the I/O part 5 includes alogic block 6 and anoutput buffer block 7. For example, thelogic block 6 includes anESD protection circuit 6 a (shown inFIG. 4 ), an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to theoutput buffer block 7. - As shown in
FIG. 4 , theoutput buffer block 7 includestransistors diodes resistance 12 for ESD protection. For example, thetransistor 8 is a P-channel MOS transistor and thetransistor 9 is an N-channel MOS transistor. - The
diodes transistor 8 is coupled with the supply voltage VCCQ and the other coupling end of thetransistor 8 is coupled with one coupling end of theresistance 12. - The other coupling end of the
resistance 12 is coupled with one coupling end of thetransistor 9 and the other coupling end of thetransistor 9 is coupled with the reference potential VSSQ. The junction of thediode 10, a first diode, and thediode 11, a second diode, and the junction of the other coupling end of theresistance 12 and the one coupling end of thetransistor 9 form an output part for theoutput buffer block 7 which is coupled with a pad 2 (orpad 2 a). - Also, as shown in
FIG. 3 , thetransistor 8 is located nearest to the periphery of thesemiconductor chip 1 in the I/O part 5. When seen in the plan view (FIG. 3 ), theresistance 12 lies above thetransistor 8 and thediodes resistance 12. - The
transistor 9 lies above thediodes logic block 6 lies above thetransistor 9 with the padlead part 5 a, for example, formed in a metal wiring layer between them. -
FIG. 5 shows the arrangement of go-round power-supply wires formed over the I/O part 5 shown inFIG. 3 . - From top to bottom in
FIG. 5 , the go-round power-supply wires are arranged as follows: go-round wire forcore supply voltage 13, go-round wire forcore reference potential 14, go-round wires for I/O supply voltage 15, and go-round wires for I/O reference potential 16 are arranged over thelogic block 6; and go-round wires for I/O reference potential 17 and go-round wires for I/O supply voltage 18 are arranged over theoutput buffer block 7, with the padlead part 5 a between the two groups of go-round wires. - The go-round wire for
core supply voltage 13 feeds the supply voltage to thecore region 4 and the go-round wire for core reference potential 14 feeds the reference potential to thecore region 4. The go-round wires for I/O supply voltage O part 5 and the go-round wires for I/O reference potential 16 and 17 feeds reference potential VSSQ to the I/O part 5. -
FIG. 6 shows the position of thepad 2 coupled with the I/O part 5 shown inFIG. 5 . - This
pad 2 is one of the pads located on the outer side (the peripheral side of the semiconductor chip 1) among thepads 2 arranged in a staggered pattern and thepad 2 is in such a position that it does not protrude from the short edge of the I/O part 5 on the peripheral side of thesemiconductor chip 1. -
FIG. 7 is a sectional view of the I/O part 5 shown inFIG. 3 . - In the device formation layer at the bottom, the
logic block 6, and thetransistor 9,diode 11 anddiode 10,resistance 12 andtransistor 8 of theoutput buffer block 7 are formed from left to right inFIG. 7 . - In the wiring layer lying over the device formation layer, the go-round wire for
core supply voltage 13, the go-round wire forcore reference potential 14, go-round wires for I/O supply voltage 15, go-round wires for I/O reference potential 16, go-round wires for I/O reference potential 17, and go-round wires for I/O supply voltage 18 are formed from left to right inFIG. 7 . - In the pad formation layer, the pad
lead part 5 a andpad 2 are formed. The padlead part 5 a andpad 2 are so formed that they lie over theoutput buffer block 7 formed in the device formation layer. - The transistor 9 (indicated by the dotted line circle in
FIG. 4 ) is manufactured in a way that a conductive film is not formed in part of the diffusion layer, in order for the drain of thetransistor 9 to have a high resistance. -
FIG. 8 is a plan view of thetransistor 9, combined with a sectional view thereof. - For example, in the
transistor 9, a P-well 19 is formed over a semiconductor substrate, and an N+type semiconductor region 20 functioning as a drain and an N+type semiconductor region 21 functioning as a source are formed on the right and left over the P-well 19. - Formed over the N+
type semiconductor region 21 is a conductive film which is ametal silicide 22 such as cobalt silicide or nickel silicide. On the other hand, ametal silicide 23 is formed over the N+type semiconductor region 20 as well, though theregion 20 is not all covered by themetal silicide 23 unlike the N+type semiconductor region 21 and themetal silicide 23 is only formed over part of theregion 20 which is coupled with a via 25 for coupling with awire 24 formed in the overlying wiring layer. - As a consequence, the sheet resistance can be increased, for example, to a level approximately 10 to 50 times higher than when a metal silicide is formed all over the N+
type semiconductor region 20. In addition, agate 26 is formed over the P-well 19 through an insulating film such as silicon oxide. - Due to the absence of the
metal silicide 23 over part of the N+type semiconductor region 20 as mentioned above, the drain terminal can have a high resistance so that thetransistor 9 is protected from ESD. -
FIG. 9 is a circuit diagram of an ordinary I/O part 50 which the present inventors have examined. - The I/O part 50 (shown in
FIG. 10 ) includes a logic block 51 (FIG. 10 ) and anoutput buffer block 52. For example, thelogic block 51 includes an ESD protection circuit, an input buffer block for input buffer, a level shifter for voltage level shift, and an inverter for sending a drive signal to theoutput buffer block 52. - The
output buffer block 52 includestransistors diodes resistances - For example, the
transistor 53 is a P-channel MOS transistor and thetransistor 54 is an N-channel MOS transistor. Thediodes - One coupling end of the
transistor 53 is coupled with the supply voltage VCCQ and the other coupling end of thetransistor 53 is coupled with one coupling end of theresistance 57. The other coupling end of theresistance 57 is coupled with one coupling end of theresistance 58 and the other coupling end of theresistance 58 is coupled with one coupling end of thetransistor 54. - The other coupling end of the
transistor 54 is coupled with the reference potential VSSQ. The junction of thediode 55 anddiode 56 and the junction of theresistance 53 andresistance 54 are coupled with a padlead part 59 which forms an output part for theoutput buffer block 52. -
FIG. 10 shows the layout of theoutput buffer block 52 in the I/O part 50 shown inFIG. 9 . - When seen in the plan view (
FIG. 10 ), in the I/O part 50, thelogic block 51 lies in an upper part of the figure and thetransistor 54 of theoutput buffer block 52 lies below thelogic block 51. Theresistance 58 lies below thetransistor 54 and thediode 56 lies below theresistance 58. - The
diode 55 lies below thediode 56 with the padlead part 59 between them. Theresistance 57 lies below thediode 55 and thetransistor 53 lies below theresistance 57. - In this circuit configuration, the pad
lead part 59 to be coupled with apad 60 can only be placed between theresistance 57 andresistance 58 and as a consequence, the padlead part 59 should be located off the center of the I/O part 50, resulting in a protrusion from the short edge of the I/O part 50 as shown on the left inFIG. 11 . This leads to a larger semiconductor chip. - On the other hand, in the case of the I/
O part 5, the structure of thetransistor 9 shown inFIG. 8 eliminates the need for a resistance equivalent to theresistance 58 and permits the pad 2 (orpad 2 a) through the drain of thetransistor 9 to be on the same node, so the padlead part 5 a can be disposed almost in the center of the I/O part 5 as shown on the right inFIG. 11 . - Since the pad
lead part 5 a is located almost in the center of the I/O part 5, as shown inFIG. 12 , thepads 2 on the outer side (on the peripheral side of the semiconductor chip 1) among the pads arranged in a staggered pattern can be moved toward the center of thesemiconductor chip 1 and theinner pads 2 a located nearer to the center of thesemiconductor chip 1 than thepads 2 can be moved toward the outer peripheral side of thesemiconductor chip 1. - Therefore, the
pads O part 5 without the need for decreasing the size of thepads - In addition, since the
diodes resistance 12 are placed between thetransistors transistors - Consequently, according to the first embodiment, the protection circuit in the
output buffer block 7 can be smaller. - Furthermore, since the
pads O part 5, the chip area of thesemiconductor chip 1 can be decreased, making it possible to realize a smaller and low-cost semiconductor integrated circuit device. - Although the
transistor 9,diode 11,diode 10,resistance 12 andtransistor 8 are arranged in order from top to bottom when seen in the plan view ofFIG. 3 in the first embodiment, the order of arrangement may be altered. - The layout of the output buffer block may be altered as follows: the
diode 11,diode 10,transistor 9,resistance 12, andtransistor 8 are arranged from top to bottom as shown inFIG. 13 or thediode 10,transistor 9,diode 11,resistance 12, andtransistor 8 are arranged from top to bottom as shown inFIG. 14 . -
FIG. 15 is a circuit diagram showing an example of the configuration of anoutput buffer block 7 according to a second embodiment of the present invention andFIG. 16 shows an example of the layout of the output buffer block shown inFIG. 15 . - In the second embodiment, the
semiconductor chip 1 is the same as the one shown inFIG. 1 in the aforementioned embodiment except the structure of theoutput buffer block 7 provided in the I/O part 5. As shown inFIG. 15 , theoutput buffer block 7 includesdiodes transistors - The
diodes transistor 8 a, a P-channel MOS transistor, is coupled with the supply voltage VCCQ and the other coupling end of thetransistor 8 a is coupled with one coupling end of thetransistor 9, an N-channel MOS transistor. - The other coupling end of the
transistor 9 is coupled with the reference potential VSSQ. The junction of thediode 10 anddiode 11, and the junction of thetransistor 8 a andtransistor 9 form an output part for theoutput buffer block 7 which is coupled with apad 2 orpad 2 a. - In this structure, not only in the
transistor 9 but also in thetransistor 8 a, a metal silicide film is not formed over part of the upper surface of the N+ type semiconductor region which functions as a drain, so that the drain terminal has a high resistance. - Consequently, since the drain terminal of the
transistor 8 a can have the same function as the resistance 12 (FIG. 4 ), theresistance 12 is no longer needed. -
FIG. 16 illustrates an example of the layout of the I/O part 5. - When seen in the plan view (
FIG. 16 ), in the I/O part 5, thelogic block 6 lies in an upper part of the figure and thetransistor 9 lies below thelogic block 6 with the padlead part 5 a between them. Thediodes transistor 9, and thetransistor 8 a lies below the diodes. - In this case as well, the pad
lead part 5 a can be located almost in the center of the I/O part 5, so the chip area of the semiconductor chip 1 (FIG. 1 ) can be smaller. This also eliminates the need for the resistance 12 (FIG. 4 ), which means that the circuit of theoutput buffer block 7 can be even smaller. - The layout of the
output buffer block 7 as shown inFIG. 16 may be varied as follows: for example, as show inFIG. 17 , thediodes transistor 8 a andtransistor 9 and their positions are reversed or as shown inFIG. 18 , thediodes logic block 6 and thetransistor 9 with the padlead part 5 a between them. - Another possible layout of the
output buffer block 7 is that as shown inFIG. 19 , the padlead part 5 a lies between thediodes transistor 9 or as shown inFIG. 20 , the padlead part 5 a lies between thediode 11 anddiode 10. -
FIG. 21 is a circuit diagram showing an example of an output buffer block according to a third embodiment of the present invention andFIG. 22 shows an example of the layout of the output buffer block shown inFIG. 21 . - In the third embodiment, as shown in
FIG. 21 , the circuit of the output buffer block includes aresistance 27 in addition to thediodes transistors FIG. 15 . - One coupling end of the
resistance 27 is coupled with the junction of thediodes resistance 27 is coupled with the junction of thetransistor 8 a andtransistor 9. The other elements are coupled in the same way as those in the second embodiment as shown inFIG. 15 . -
FIG. 22 illustrates an example of the layout of the I/O part 5. - When seen in the plan view (
FIG. 22 ), in the I/O part 5, thelogic block 6 lies in an upper part of the figure and thediode 10 anddiode 11 lie below thelogic block 6 with the padlead part 5 a between the logic block and the diodes. - The
resistance 27 lies below thediode 11 and thetransistor 9 lies below theresistance 27, and thetransistor 8 lies below thetransistor 9. - In this case as well, the pad
lead part 5 a can be located almost in the center of the I/O part 5, so the chip area of the semiconductor chip 1 (FIG. 1 ) can be smaller. - The layout of the
output buffer block 7 as shown inFIG. 22 may be varied as follows: for example, as shown inFIG. 23 , the positions of thetransistor 8 a andtransistor 9 are reverse to those shown inFIG. 22 . - The invention made by the present inventors has been so far detailed in reference to the preferred embodiments thereof. However, the invention is not limited to such embodiments and it is obvious that these details may be modified in various ways without departing from the spirit and scope of the invention.
- The present invention is suitable as a chip area reduction technique for semiconductor integrated circuit devices with a “PAD on I/O (Input/Output)” cell structure.
Claims (11)
1-10. (canceled)
11. A semiconductor integrated circuit device comprising a semiconductor chip, the semiconductor chip comprising:
a core region including logic circuits having semiconductor elements;
an I/O region arranged around the core region;
a plurality of I/O pads formed in the I/O region; and
a plurality of I/O parts formed in the I/O region and disposed along an edge of the semiconductor chip, each of the I/O parts coupled with an associated one of the I/O pads,
the I/O parts each comprising:
an output buffer block including an output buffer to function as an interface for output of signal to the outside, the output buffer including a first transistor and a second transistor;
a logic block configured to control the output buffer; and
a pad lead part disposed between the logic block and the first transistor, and coupled to the associated one of the I/O pads,
wherein, in each of the I/O parts:
in plan view, the logic block, the pad lead part, the first transistor and the second transistor are arranged in this order starting from a position closer to a center of the semiconductor chip toward the edge of the semiconductor chip,
the pad lead part is coupled with a connection part of a drain terminal of the first transistor and a drain terminal of the second transistor,
in the first transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain,
in the second transistor a conductive film is not formed over part of a main surface of a semiconductor region functioning as a drain.
12. The semiconductor integrated circuit device according to claim 11 ,
wherein conductivity of the first transistor is different from conductivity of the second transistor.
13. The semiconductor integrated circuit device according to claim 11 ,
wherein the output buffer block includes a first and a second diode for ESD protection, and
wherein both the first and the second diodes are coupled to the connection part of the drain terminal of the first transistor and the drain terminal of the second transistor.
14. The semiconductor integrated circuit device according to claim 13 ,
wherein the first and the second diodes are arranged between the first transistor and the second transistor.
15. The semiconductor integrated circuit device according to claim 13 ,
wherein the first and the second diodes are arranged between the first transistor and the pad lead part.
16. The semiconductor integrated circuit device according to claim 13 ,
wherein the first and the second diodes are arranged between the logic block and the pad lead part.
17. The semiconductor integrated circuit device according to claim 13 ,
wherein the first diode is arranged between the logic block and the pad lead part, and
wherein the second diode is arranged between the pad lead part and the first transistor.
18. The semiconductor integrated circuit device according to claim 11 ,
wherein the output buffer block further comprises a resistor, and
wherein the pad lead part is coupled with the connection part of the drain terminal of the first transistor and the drain terminal of the second transistor through the resistor.
19. The semiconductor integrated circuit device according to claim 18 ,
wherein the resistor is arranged between the pad lead part and the first transistor.
20. The semiconductor integrated circuit according to claim 11 ,
wherein the I/O pads comprise a plurality of first I/O pads and a plurality of second I/O pads,
wherein each of the first I/O pads is arranged closer to the center of the semiconductor chip than the pad lead part so as to be overlapped with the logic block of a corresponding one of the I/O parts in plan view, and
wherein each of the second I/O pads is arranged closer to the edge of the semiconductor chip than the pad lead part so as to be overlapped with the output buffer block of a corresponding one of the I/O parts in plan view.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/918,659 US20180197850A1 (en) | 2008-12-19 | 2018-03-12 | Semiconductor integrated circuit device |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008323589A JP2010147282A (en) | 2008-12-19 | 2008-12-19 | Semiconductor integrated circuit device |
JP2008-323589 | 2008-12-19 | ||
US12/642,760 US20100155845A1 (en) | 2008-12-19 | 2009-12-18 | Semiconductor integrated circuit device |
US13/910,891 US9947651B2 (en) | 2008-12-19 | 2013-06-05 | Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal |
US15/918,659 US20180197850A1 (en) | 2008-12-19 | 2018-03-12 | Semiconductor integrated circuit device |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US13/910,891 Continuation US9947651B2 (en) | 2008-12-19 | 2013-06-05 | Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal |
Publications (1)
Publication Number | Publication Date |
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US20180197850A1 true US20180197850A1 (en) | 2018-07-12 |
Family
ID=42264782
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/642,760 Abandoned US20100155845A1 (en) | 2008-12-19 | 2009-12-18 | Semiconductor integrated circuit device |
US13/910,891 Active US9947651B2 (en) | 2008-12-19 | 2013-06-05 | Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal |
US15/918,659 Abandoned US20180197850A1 (en) | 2008-12-19 | 2018-03-12 | Semiconductor integrated circuit device |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
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US12/642,760 Abandoned US20100155845A1 (en) | 2008-12-19 | 2009-12-18 | Semiconductor integrated circuit device |
US13/910,891 Active US9947651B2 (en) | 2008-12-19 | 2013-06-05 | Semiconductor integrated circuit device having an NMOS with a high resistance drain terminal |
Country Status (3)
Country | Link |
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US (3) | US20100155845A1 (en) |
JP (1) | JP2010147282A (en) |
TW (2) | TWI593031B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11824055B2 (en) | 2019-11-06 | 2023-11-21 | Socionext Inc. | Semiconductor integrated circuit device |
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JP2012104552A (en) * | 2010-11-08 | 2012-05-31 | Panasonic Corp | Semiconductor integrated circuit |
JP5896682B2 (en) * | 2011-10-18 | 2016-03-30 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
EP2777780B1 (en) * | 2011-11-08 | 2021-08-25 | Sony Group Corporation | Sensor device, analyzer, and storage medium |
KR101675121B1 (en) | 2011-12-30 | 2016-11-10 | 인텔 코포레이션 | Wrap-around trench contact structure and methods of fabrication |
KR20150058273A (en) * | 2012-09-26 | 2015-05-28 | 베이샌드 인코퍼레이티드 | Flexible, space-efficient i/o circuitry for integrated circuits |
WO2016203648A1 (en) * | 2015-06-19 | 2016-12-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP6118923B2 (en) * | 2016-01-26 | 2017-04-19 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
TWI582940B (en) * | 2016-06-20 | 2017-05-11 | 台灣類比科技股份有限公司 | Integrated circuit and layout structure of output buffer with an esd self-protection of the same |
CN107564902A (en) * | 2016-07-01 | 2018-01-09 | 台湾类比科技股份有限公司 | Integrated circuit and its output buffer layout structure for having self electrostatic protection |
JP6793025B2 (en) * | 2016-12-07 | 2020-12-02 | 日立オートモティブシステムズ株式会社 | Semiconductor device |
JP2018186144A (en) * | 2017-04-25 | 2018-11-22 | 株式会社村田製作所 | Semiconductor device and power amplifier module |
JPWO2022215485A1 (en) * | 2021-04-08 | 2022-10-13 | ||
WO2024047820A1 (en) * | 2022-08-31 | 2024-03-07 | 株式会社ソシオネクスト | Semiconductor integrated-circuit device |
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2009
- 2009-11-20 TW TW104114956A patent/TWI593031B/en active
- 2009-11-20 TW TW098139554A patent/TWI496225B/en active
- 2009-12-18 US US12/642,760 patent/US20100155845A1/en not_active Abandoned
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2013
- 2013-06-05 US US13/910,891 patent/US9947651B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
US9947651B2 (en) | 2018-04-17 |
TW201029079A (en) | 2010-08-01 |
TWI496225B (en) | 2015-08-11 |
JP2010147282A (en) | 2010-07-01 |
US20130264647A1 (en) | 2013-10-10 |
TW201532162A (en) | 2015-08-16 |
TWI593031B (en) | 2017-07-21 |
US20100155845A1 (en) | 2010-06-24 |
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