JPS59215743A - Large scale integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to form a large scale integrated circuit device finished with valuation of the faculty and the characteristic together in one chip as it is by a method wherein wiring material layers are formed on the top portion of wiring layers used for formation of chip corresponding regions of the plural number of pieces interposing an interlayer insulating film between them. CONSTITUTION:Metal wiring layers 17, 27 are formed interposing an interlayer insulating film 26 between them, and the metal wiring layer 27 of the second layer thereof are used as mutual wirings 6 between chip corresponding regions A, B and outside wirings 7. Signals to be transmitted according to the wirings 27 may be limited only to the input/output signals of the respective regions A, B. Moreover electric connection between the wiring 27 and inner bonding pads formed on the first layer metal layers can be attained through pierced contacts 28 formed by removing the film 26 only at the necessary parts to form interlayer contact holes. At the LSI constructed in such a way, the wiring 27 can be formed on the regions A, B, and because to provide especially a wiring region is not necessary, chip size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a large-scale integrated circuit device that has a simplified system configuration such as a data processing device.

[Technical background of the invention and its problems]

To configure a system such as a nocusonal computer, a plurality of LSIs (Large Scale Integrated Circuits) are usually used in combination. These are the CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), key control section, serial input/output section, parallel input/output section, counter timing control section, There are many chips such as a display drive section, and interconnections between the chips are made on a printed circuit board. However, with this method, the interconnections on the printed circuit board are complicated, requiring time and effort to manufacture, which increases costs.Also, because the capacitance of the printed wiring is large, the speed of each chip increases. However, this does not lead to speeding up the entire system.Also, due to the high failure rate, there is a very strong demand from users that it is possible to combine multiple LSIs used in the system into a single chip.

Methods to meet the above demand for single-chip LSI include (c) redesigning the entire system to create a new single-chip LSI, and ←) encapsulating multiple chips in a single chip or cage. 1 hybrid IC (integrated circuit),
etc. can be considered. In the case of the method of redesigning the entire system as described in item 0), the currently available design methods include: ■ Complete manual design method, ■ Automated design method using a building block method using four frost calculators, ■ Gate array, etc. automatic cutting, etc. All of these ■～■ have advantages/
Although there are disadvantages, the biggest disadvantage of redesigning is that ``each chip has already been developed and has been sufficiently evaluated in terms of function and characteristics, but it is necessary to design and design the same chip again. .

The evaluation process must be repeated again.'' Therefore, there is a risk of design errors, and there are various problems with the tube, which takes time to develop, so it must be said that this method is ineffective.

The hybrid IC method described in item (b) above only appears as a single component when viewed from the outside, and is simply a smaller version of the method of mounting and wiring multiple chips on the printed circuit board. . Of course, there are advantages to just making it smaller, but as an actual implementation technology, there are still doubts as to how many chips can be hybridized, and even if it were possible, the cost would increase considerably. Will.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is intended to provide a large-scale integrated circuit device that enables a new system different from either town planning or hybridization to be integrated into a single chip.

[Summary of the invention]

In the present invention, in order to realize a desired device, the patterns of each chip that have already been designed and evaluated are used as they are to form a single chip.

[Embodiments of the invention]

Embodiments of the present invention will be explained below with reference to the drawings. 1st
In the figure, 1 is a semiconductor chip, and A and B are areas for chip 1 that were formed together in the same process in chip 1, and these areas were previously evaluated as chip A and chip B, respectively.

2.3 is the chip equivalent area A, and B is the former chip A.

4 is the bonding pad under the bonding pad (temporarily referred to as the inner bonding pad) at B, and 4 is the bonding pad of chip 1 (this is tentatively referred to as the outer pumping pad). In this way, place the chip equivalent areas A and B, which have already been evaluated, with an appropriate space 5, and place the chip 1.
Place and form within. This space 5 is the chip equivalent area A
, B. Also, near the periphery of the chip, there is wiring with a bonding pad (temporarily referred to as external wiring) for connection to the outside as a lead terminal from the LSI after it is integrated into a single chip. ) 7 is also provided. That is, the mutual arrangement M! between the chip equivalent areas A and 8! 6 is made of a wiring layer (polysilicon, aluminum, etc.) by the process of regions A and H using the wiring region 5 between the corresponding bonding pads that each region A and B have. Furthermore, the necessary number of pumping pads 4 corresponding to the external wiring 7 are laid out around the chip, and the external wiring 7 is connected to the pumping pads 2, 4 in the corresponding areas A and H.
The pad between the pad 3 and the outer bonding pad 4 is made of polysilicon, aluminum, or the like.

FIG. 2 shows a partial cross section of FIG. 1, where 1j is a transistor region of the chip equivalent area A or B, 12 is an N-type substrate, 13.14 is a P-type source and drain region, 15 is an insulating film, 16 is a polysilicon gate electrode, 17 is an aluminum wiring, 18 is a wiring crossing area in the wiring area 5;
1+172 is an aluminum wiring layer corresponding to the wiring 6 in FIG. 1, and 19 is a polysilicon recording layer.

The above example is a method of actually realizing the mutual wiring and external wiring in the area corresponding to each chip by providing the wiring area 5 without changing the wafer process of each chip. In other words, the printed circuit board is printed on the same board as the chip with a wiring area above it, and the chip size after making it into one chip is the total area of each chip equivalent area A and B plus the wiring area of 5 minutes. However, the following examples are shown in Figures 1, 2, and 2.
This is an embodiment of the present invention, which is an improvement on the example shown in the figure, and uses a one-chip reduction method that can reduce the wiring area 5 to zero from the beginning.

Figures 3 and 4 show examples of this, but here, to simplify the explanation, chip-equivalent regions A and B are each formed using a silicon gate process as in the case of Figures 1 and 2. It is assumed that this is a configured LSI. Therefore, chip equivalent area A
, B are wiring layers of three types: an impurity diffusion layer (P, N diffusion, etc.) that forms the source and drain, a polysilicon layer that forms the gate electrode, and a metal wiring layer that is often used as the normal layer. 1, and they are electrically insulated and coupled on chips A and B depending on the circuit configuration. The input signals and output signals of the chip-equivalent areas A and B are usually connected to the leads of the bonding pad 4 placed around the chip and to the leads of the LSI.
connected to the outside. The bonding/maintenance is usually formed from a metal layer.

Fig. 4 shows a partial cross-section of Fig. 3, but since this is an example of a case corresponding to Fig. 2, corresponding parts are given the same reference numerals, explanations are omitted, and features are not explained. Let me explain the points. In FIG. 4, 21 is a P well layer, 22.23 is an N well layer, and 22.23 is an N well layer.
source and drain layers of channel type transistor 25;
4 is a gate electrode made of polysilicon, 26 is an interlayer insulating film, and 27 is a second aluminum wiring layer provided on this insulating film, which corresponds to wiring 6 or 7 in FIG. . 28 is a contact for connecting aluminum wires fg1y and 2v.

In this way, the method shown in FIGS. 3 and 4 uses the method shown in FIG. ．． ? 7 is formed, and this second metal wiring layer is used as mutual wiring 6 and external wiring 7 between the chip-equivalent area and B. Second layer metal wiring 22
The signals required are only input/output signals (including power supply) for each of the chip equivalent areas A and B. Also, the second layer metal wiring 2
7 and the inner bonding pad formed by the first layer of metal, this can be done by removing the interlayer insulating film 26 only at the necessary parts using photolithography, and forming a contact hole between the holes ρ. This can be done by creating.

Such a contact 28 is usually a via contact (V
IA contact). That is, a via contact is formed on the pumping layer 2 or 3, and a second layer of metal (aluminum) is deposited thereon, thereby connecting the metal wirings of each layer. It is clear, however, that the contact need not necessarily be formed on the bond/quarter 2 or 3. A new LSI in which chip-equivalent areas A and B are combined will eventually become an LS
A bonding pad (outer bonding pad) 4 is required for transmitting signals to the outside, but this is formed from the second layer of metal.

In the LSI configured as shown in FIGS. 3 and 4, the second layer of wiring 27 can be formed on the chip-equivalent areas A and B, and especially in the wiring area 27 as in the case of FIG. Since there is no need to specifically provide a chip, the chip size can be reduced. Also the first
Since aluminum can be used at the intersection of the first layer and the second layer wiring, the resistance can be kept low and high-speed design is possible. Further, since the first layer wiring 17 and the second layer wiring 27 often intersect on the same plane, the degree of freedom in wiring design is increased.

FIG. 5 shows an example of pattern arrangement using the methods shown in FIGS. 3 and 4. A-E is an LSI (chip-equivalent area) that has already been developed and whose functions are guaranteed, and the same chip-equivalent area is N.
It is a double turn (for example, D=E). Further, the wiring between each chip-corresponding area is formed by a second layer of aluminum wiring 22 (corresponding to wiring 6 or 7 in FIG. 5). Pads 2, 3 and the second IP which each chip equivalent area originally has! The first wirings 6 and 7 are connected through via contacts.

The outer circumferential node 4 serves as the new LSI's bonding pad, and is made from the second layer of aluminum.

Note that the present invention is not limited to the embodiments, and can be applied in various ways. For example, in the embodiment, chip equivalent candy area A,
Although the case where the structure of B etc. is a silicon gate type has been described, it can be applied to other cases such as an aluminum gate type, a dungesten gate type, a molybdenum gate type, etc. Further, as the metal material for the wiring, not only aluminum but also tungsten, molybdenum, and various other materials can be used. In addition, in the embodiment, the outer pumping pad 4 is formed in the outer region of the chip-equivalent regions A', H, but if the glossy turn shape permits, it may be formed on the same line as the pumping pads z, 3 of the chip-equivalent regions A', H. A motherboard 4 may also be formed. Furthermore, although the case of two-layer wiring using aluminum as the metal wiring layer has been described, multi-layer wiring such as three-layer or four-layer wiring may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, since the chip-equivalent area requires almost no modification to the conventional chip configuration, a device whose functions and characteristics have been evaluated can be made into a single chip as is. Furthermore, since it can be made into a single chip, reliability is improved compared to those using conventional printed circuit boards. Furthermore, the conventional Unihachi process can be used as is to obtain this device, and the manufacturing process can be simplified. Further, since the second and subsequent layers of wiring can be formed on the chip-equivalent region, the chip size can be reduced. Also number 1. Since aluminum can be used for the cross-wiring portions such as the second layer, resistance can be reduced and crystal speed can be designed. Furthermore, since the wiring in the second and subsequent layers does not intersect with that in the first layer on the same plane, the degree of freedom in wiring design is increased.

[Brief explanation of drawings]

Figure 1 shows 41! of the LSI before improvement. ' is a schematic plan view, Fig. 2 is a partial sectional view thereof, Fig. 3 is a schematic plan view of an embodiment of the present invention, Fig. 4 is a partial sectional view thereof, and Fig. 5 is an application of the above embodiment. FIG. 3 is a schematic plan view showing an example. 1°...Semiconductor chip, 2~4...Bondeia Rit
4 pad, 6, 7... Wiring, 12... N type board, 17
゜22... Wiring, 21... P well layer, 26...
Interlayer insulating film, 28... Via contact, A, B...
・Chip equivalent area. Applicant's representative Patent attorney Suzue Takeshi Buta.

Claims (1)

[Scope of Claims] (11) A plurality of chip-equivalent regions necessary for performing the functions of a plurality of integrated circuits whose functions have already been confirmed, and a mutual derivation of each of the chip-equivalent regions to outside the region. A wiring material is provided that selectively connects between the electrodes or between the electrodes and the bonding pad, and the wiring material is placed on the upper layer of the wiring #i1 layer used to form the plurality of chip-equivalent regions. A large-scale integrated circuit device in which the plurality of integrated circuits, each of which is formed via an interlayer insulating film, are configured as one chip on the same semiconductor substrate. (2) Each of the chip-equivalent areas is The large-scale integrated circuit device according to item 1 of the scope of the patent application, which is a independently completed CPU (central processing unit), memory, or peripheral device. (3) The chip-equivalent region is formed with a silicon gate structure. (4) The large-scale integrated circuit device according to claim 1, wherein the chip-equivalent region is formed of an aluminum gate structure. ( 5) A large-scale integrated circuit device according to claim 1, characterized in that the wiring material has a wiring nf structure with two or more layers. (6) A plurality of LSIs whose functions have already been confirmed. a step of simultaneously forming chip-equivalent regions of the number of channels necessary to perform the ω function on the same semiconductor substrate; a step of forming an interlayer insulating film of a wiring layer on the chip-equivalent region;
It is characterized by comprising a step of selectively connecting between the wiring lines for leading out of the area of each chip equivalent area or between the electrodes and the bonding pads with an electrode wiring layer provided on the interlayer insulating film. A method for manufacturing a large-scale integrated circuit device. (7) The large-scale integrated circuit device according to claim 6, wherein each of the chip [4''+ITJ areas is a cpv (-4 central processing unit), memory, or peripheral device completed independently. Manufacturing method. (8) The method for manufacturing a large-scale integrated circuit device according to claim 6, wherein the chip-equivalent region is formed of a silicon gate structure. (9) The chip-equivalent region is formed of an aluminum gate (
10) The method for manufacturing a large-scale integrated circuit device according to claim 6, wherein the electrode wiring layer has a wiring structure of two or more layers.