JPS62194640A - Semiconductor integrated circuit using bump mounting - Google Patents

Abstract

PURPOSE:To fine a chip for a gate array LSI on practical effect, and to shorten mean wiring length by dispersion and arranging a large number of bumps onto the whole surface of the semiconductor chip, disposing I/O gate cells for a gate array around the chip and along lines partitions the surface of the chip into the plural and arranging internal gate cells into the partitioned regions. CONSTITUTION:Bumps 10 are dispersed and arranged on the whole surface of a chip 12, I/O gate cells 14 are disposed around the chip and on lines dividing the inside of the chip, and internal gate cells are arranged into a region 16 surrounded by the I/O gate cells 14. The chip 12 is divided into a number such as two, an I/O gate cells array is formed to an eight shape, and the internal gate cells are disposed in the two internal regions. Accordingly, the chip in large size is formed to a shape that the chips in small size divided into two or four ... are collected, and an LSI in which the I/O gates are arranged around the chips in small size and the internal gates in the I/O gates is manufactured, thus shortening mean wiring length.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit using bump mounting, and more particularly to a method for laying out bumps and outer and inner gate cells on a chip.

[Conventional technology]

Wire bonding is widely used in semiconductor integrated circuits to connect semiconductor chips to terminal pins of packages. In this case, a large number of bonding pads are provided around the semiconductor chip, and a large number of bonding pads are also provided on the package substrate to connect with terminal pins.
Each of these pads is connected by a wire.

Gate array LSI has many external gates (
An I/O gate) and an internal gate are created, but in the wire bonding method, the internal gate is created in the center of the chip, and the I/O gate is created in the annular area between the bonding pad and the internal gate. .

A bump method is also used to connect the chip and its mounting board. This is multiple hemispherical nodules (bumps) on the chip.
A plurality of pads are made on the substrate side, and the chip and the substrate are connected by bonding these bumps to the pads (soldering by heating if they are solder bumps).

This bump method is used not only for individual components, but also for integrated circuits.

[Problem that the invention seeks to solve]

By the way, in a gate array LSI, the arrangement of I/O gate cells and internal gate cells greatly affects the chip size and performance of the LSI. In gate array LSIs in which bonding pads or bumps are placed on the periphery of the chip, internal gates are placed in the center of the chip, and I/O gates are placed between them, the wiring length on the chip may become long, which adversely affects the chip size and/or performance. effect. The present invention attempts to improve this point by changing the layout of the I/O ψ ports.

[Means for solving problems]

A semiconductor integrated circuit using bump mounting according to the present invention has a large number of bumps distributed over the entire surface of a semiconductor chip, and I/O gate cells of a gate array are arranged along lines dividing the periphery of the chip and the chip surface into a plurality of parts. The device is characterized in that the internal gate cells are arranged inside the divided regions.

[Effect]

In the present invention, the bumps/O are connected to the chip 12 as shown in FIG.
The I/O gate cells 14 are arranged on a line that separates the periphery of the chip from the inside thereof, and the internal gate cells are arranged within a region 16 surrounded by the I/O gate cells 14. In this example, the chip 12 is divided into two parts, the I/O gate cell array is shaped like a figure eight, and the internal gate cells are divided into two parts.
located in two internal areas. Of course, instead of dividing into two, it may be divided into four, eight, etc.

In this way, even large chips can be divided into two parts or four parts.
Division... It becomes a collection of small-sized chips and knobs, and an LSI with I/O gates arranged around the small-sized chip and internal gates inside, reducing the average wiring length. It becomes possible. It also enables high integration of internal gates.

Although the I/O gate cell 14 is shown in FIG. 1 directly below the bump/O, it may also be provided between each knob as shown in FIG. When bumps are provided on the I/O gates as shown in FIG. 1, the region between each 1/O gate cell becomes a channel (a region where power supply and signal lines run). In the case of FIG. 2, the channel is directly below the bump. Note that if there is room for the channel, an internal gate may be provided in this portion as well. Power supply wiring may have problems with potential drop (on the Vce side) or potential rise (on the Vss side) due to IR drop, but as a countermeasure to this problem, the package has multiple power supply terminal pins, and as a result, the chip's power supply bonding pad or There may also be multiple bumps. The hatched bumps in FIGS. 1 and 2 are for power supply, and a plurality of bumps are provided. Since each bump has a permissible current value, it is necessary to have a plurality of bumps from this point of view as well. Bumps without diagonal lines are for signal output.

〔Example〕

In the gate array LSI, the connection between the E/O buffer and the internal gate is as shown in FIG. Figure 3 (
It has the structure shown in b). That is, each consists of a differential pair consisting of two transistors whose emitters are commonly connected to a constant current source transistor, and a pair of output stage transistors whose bases are connected to the load resistor.
In 4a, terminal T+ is for input, T2 is for reference voltage VBB,
Terminal T3. T4 is for output. Further, in the internal gate 18, terminal T5 is for input, T6 is for reference voltage Vr, T7. T
ll is for output, and in the output buffer 14b, terminal T9 is for input, TXo is for reference voltage Vr, and terminal T11
*TI2 is for output. VO2 is the voltage that determines the current value of the constant current source transistor.The configuration of the output buffer and internal gate is the same, but the reference voltage is different, the drive ability of the input buffer is greater than that of the internal gate, and the output Buffers are larger than these.

FIG. 4(a) is a diagram showing the structure inside the I/O gate 14,
In the region 14a, components for one output buffer and its reference voltage Vr generation circuit are formed, in the region 14b, components for two input buffers, and in the region 14c, the reference voltage VBB and the reference voltage Vr. The components of the generator circuit (for high drive, which is used in place of VBB) are made. FIGS. 4(b) and 4(c) show element arrays constructed in regions 14b and 14c.

FIG. 5 (al indicates the configuration of the internal gate 18. In the center of this area, the constituent elements of the reference voltage Vr generation circuit (shown in (b)) are provided, and in each of the two areas on both sides, there are three /Constituent elements of internal gate circuits such as NOR circuits ((C)
) are provided respectively.

When a bump/O is formed on the I/O gate 14 as shown in FIG. 1, it becomes as shown in FIG.

That is, a transistor is formed on a semiconductor substrate (chip) STJB, each electrode wiring of emifter E1 base B1 collector C is attached, a pad of aluminum A/ is attached to the base electrode wiring which becomes the input end, and a cover film psc is attached around it. A bump is formed on this pad. To form a bump, as shown in Figure 7 (al), you can apply a barrier metal on the A7! pad, place a solder ball on top of it, and heat it to form a bump, or solder plate it on the barrier metal. Another method is to make a solder block, remove the resist, and then heat it to turn the solder block into a bump.

〔Effect of the invention〕

As explained above, according to the present invention, a chip of a bump-mounted gate array LSI can be subdivided during effective operation, thereby reducing the average wiring length, reducing the potential fluctuation of the power supply wiring, reducing the chip size, and improving the performance of the gate array. It is possible and very effective.

[Brief explanation of drawings]

1 and 2 are explanatory diagrams of the present invention, FIG. 3 is a circuit diagram showing the connection state and configuration of the internal and external gates, and FIG. 4 is an I
An explanatory diagram of the /O buffer, FIG. 5 is an explanatory diagram of the internal gate,
FIG. 6 is an explanatory diagram of the state of connection between the gate and the bump, and FIG. 7 is an explanatory diagram of the bump manufacturing procedure. In the drawing, 12 is a semiconductor chip, /O is a bump, and 14 is an I/O.
O gate cell 16 is an internal gate cell forming region.

Claims (2)

[Claims] (1) A large number of bumps are distributed over the entire surface of a semiconductor chip, I/O gate cells of a gate array are arranged along lines that divide the periphery of the chip and the chip surface into multiple parts, and internal gate cells are divided into multiple parts. 1. A semiconductor integrated circuit using bump mounting, characterized in that the semiconductor integrated circuit is disposed inside a bump mounting area. (2) A semiconductor integrated circuit using bump mounting according to claim 1, wherein the I/O gate cell is formed with elements constituting one output buffer and two input buffers.