JPH04365367A - Analog array - Google Patents

Analog array

Info

Publication number
JPH04365367A
JPH04365367A JP14197791A JP14197791A JPH04365367A JP H04365367 A JPH04365367 A JP H04365367A JP 14197791 A JP14197791 A JP 14197791A JP 14197791 A JP14197791 A JP 14197791A JP H04365367 A JPH04365367 A JP H04365367A
Authority
JP
Japan
Prior art keywords
chip
specific
aluminum wiring
transistors
circuit configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14197791A
Other languages
Japanese (ja)
Inventor
Noriyuki Ueda
植田 法幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Engineering Co Ltd
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Engineering Co Ltd, Mitsubishi Electric Corp filed Critical Mitsubishi Electric Engineering Co Ltd
Priority to JP14197791A priority Critical patent/JPH04365367A/en
Publication of JPH04365367A publication Critical patent/JPH04365367A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive to enhance an electrical characteristic by a method wherein a specific region in which elements for the purpose of a specific circuit configuration are provided within an IC chip. CONSTITUTION:Transistors 3i, 3i are respectively connected to transistors 3j, 3k through an aluminum wiring 4a within a specific region 5. Further, a transistor 3j is connected to a transistor 3b through an aluminum wiring 4b, transistors 3k, 3b, 3m are connected through an aluminum wiring 4c, and the transistor 3m is connected to a resistance 2i through an aluminum wiring 4d. Thus, the specific region 5 is provided within an IC chip 1A and each element is arranged in the specific region 5 by expecting a specific circuit configuration beforehand, whereby the wiring is readily performed and a pattern layout becomes simple. Also, each element can be so arranged as not to deteriorate a bearing characteristic. Thus, an electrical characteristic is enhanced.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】この発明は、アナログ回路を集積
化する場合等に用いて好適なアナログアレイに関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog array suitable for use in integrating analog circuits.

【0002】0002

【従来の技術】図4は従来のアナログアレイのICチッ
プのパターンレイアウトの一例を示す配置図である。図
4において、1はICチップ、2a〜2hはICチップ
内に格子状に配置された抵抗器、3a〜3hはICチッ
プ1内に格子状に配置されたトランジスタである。
2. Description of the Related Art FIG. 4 is a layout diagram showing an example of the pattern layout of IC chips in a conventional analog array. In FIG. 4, 1 is an IC chip, 2a to 2h are resistors arranged in a grid pattern within the IC chip, and 3a to 3h are transistors arranged in a grid pattern within the IC chip 1.

【0003】ICチップ1内に格子状に配列された抵抗
器2a〜2h及びトランジスタ3a〜3lを必要数だけ
アルミ配線(図示せず)で接続することにより所望の電
子回路を構成する。
A desired electronic circuit is constructed by connecting the required number of resistors 2a to 2h and transistors 3a to 3l arranged in a grid in the IC chip 1 with aluminum wiring (not shown).

【0004】0004

【発明が解決しようとする課題】従来のアナログアレイ
では、抵抗器やトランジスタなどの素子が格子状に配列
されているので、特に大規模の回路を構成するときは遠
い位置にある素子同士を結線する機会が多くなり、この
ため素子同士を結ぶアルミ配線が長くなってパターンレ
イアウトが難しくなり、又遠い位置にある素子同士は互
いにその特性が異なる傾向があり、そのためいわゆるペ
アリング特性が劣化し、IC全体の電気的特性が劣化す
る等の問題点があった。
[Problems to be Solved by the Invention] In conventional analog arrays, elements such as resistors and transistors are arranged in a grid pattern, so when configuring a large-scale circuit, it is difficult to connect elements located far apart. As a result, the aluminum wiring that connects the elements becomes longer, making pattern layout difficult, and elements that are located far apart tend to have different characteristics, which deteriorates the so-called pairing characteristics. There were problems such as deterioration of the electrical characteristics of the entire IC.

【0005】この発明は上記のような問題的を解決する
ためになされたもので、パターンレイアウトが簡単で、
電気的特性の優れたアナログアレイICを得ることを目
的とする。
[0005] This invention was made to solve the above-mentioned problems, and the pattern layout is simple.
The purpose is to obtain an analog array IC with excellent electrical characteristics.

【0006】[0006]

【課題を解決するための手段】この発明に係るアナログ
アレイは、ICチップ内に特定の回路構成を目的とする
素子を配置した特定領域を備えたものである。
[Means for Solving the Problems] An analog array according to the present invention includes a specific area in an IC chip in which elements intended for a specific circuit configuration are arranged.

【0007】また、この発明に係るアナログアレイは、
ICチップ内に特定領域を複数個備えたものである。
[0007] Furthermore, the analog array according to the present invention includes:
The IC chip has a plurality of specific areas within the IC chip.

【0008】また、この発明に係るアナログアレイは、
ICチップ内に回路機能の異なる特定の領域を複数個備
えたものである。
[0008] Furthermore, the analog array according to the present invention includes:
The IC chip has a plurality of specific areas with different circuit functions within the IC chip.

【0009】[0009]

【作用】この発明においては、ICチップ内に特定の回
路構成を目的とした素子配置の特定領域を設ける。これ
により、パターンレイアウトの簡略化、電気的特性の向
上が図かれる。
According to the present invention, a specific area for arranging elements for a specific circuit configuration is provided in an IC chip. This simplifies the pattern layout and improves electrical characteristics.

【0010】また、この発明においては、ICチップ内
に特定領域を複数個設ける。これにより、回路機能を拡
大できる。
Further, in the present invention, a plurality of specific areas are provided within the IC chip. This allows the circuit functionality to be expanded.

【0011】また、この発明においては、ICチップ内
に回路機能の異なる特定の領域を複数個設ける。これに
より、複雑な回路機能が可能となり、更に全体の回路機
能を拡大できる。
Further, in the present invention, a plurality of specific regions having different circuit functions are provided within the IC chip. This enables complex circuit functions and further expands the overall circuit function.

【0012】0012

【実施例】【Example】

実施例1.図1はこの発明の一実施例によるICチップ
のパターンレイアウトを示す配置図である。図1におい
て、図4と対応する部分には同一符号を付し、その説明
を省略する。1AはICチップ、5はICチップ1A内
に設けられ、特性の回路構成を目的とする素子を配置し
た特定領域である。2iは特定領域5内に配置された素
子としての抵抗器、3i〜3mは特定領域5内に配置さ
れた素子としてのトランジスタ、4a〜4dは特定領域
5内において各素子を接続するためのアルミ配線である
。特定領域5内において、トランジスタ3iと3jがア
ルミ配線4aにより接続されると共にトランジスタ3i
と3kがアルミ配線4aにより接続される。また、トラ
ンジスタ3jと3lがアルミ配線4bにより接続され、
トランジスタ3k,3l及び3mがアルミ配線4cによ
り接続され、更にトランジスタ3mと抵抗器2iがアル
ミ配線4dにより接続される。このように、本実施例で
は、ICチップ内に特定領域5を設け、この特定領域5
に予め特定の回路構成を想定して各素子を配置するよう
にしたので、配線が容易となり、パターンレイアウトが
簡単になる。また、各素子はペアリング特性が劣化しな
いように配置できるので、電気的特性を向上できる。
Example 1. FIG. 1 is a layout diagram showing a pattern layout of an IC chip according to an embodiment of the present invention. In FIG. 1, parts corresponding to those in FIG. 4 are given the same reference numerals, and their explanations will be omitted. 1A is an IC chip, and 5 is a specific area provided within the IC chip 1A in which elements intended for a characteristic circuit configuration are arranged. 2i is a resistor as an element arranged in the specific region 5, 3i to 3m is a transistor as an element arranged in the specific region 5, and 4a to 4d are aluminum for connecting each element in the specific region 5. It's the wiring. In the specific area 5, transistors 3i and 3j are connected by an aluminum wiring 4a, and the transistor 3i
and 3k are connected by aluminum wiring 4a. Further, the transistors 3j and 3l are connected by an aluminum wiring 4b,
Transistors 3k, 3l, and 3m are connected by aluminum wiring 4c, and transistor 3m and resistor 2i are further connected by aluminum wiring 4d. As described above, in this embodiment, the specific area 5 is provided in the IC chip, and the specific area 5 is
Since each element is arranged assuming a specific circuit configuration in advance, wiring becomes easy and pattern layout becomes simple. Moreover, since each element can be arranged so that pairing characteristics do not deteriorate, electrical characteristics can be improved.

【0013】実施例2.図2はこの発明の他の実施例に
よるICチップのパターンレイアウトを示す配置図であ
る。図2において、図1に対応する部分には同一符号を
付し、その説明を省略する。1BはICチップ、5a,
5bは夫々ICチップ1B内に設けられ、図1の特定領
域5と同様に、特定の回路構成を目的とする素子を配置
した特定領域である。ここでは特定領域5a,5bは同
一の回路機能を有するものとする。このように、本実施
例では、ICチップ内に予め特定の回路構成を想定した
各素子を配置した特定領域5a,5bを複数個設けるよ
うにしたので、上記実施例1と同様の作用効果が得られ
ると共に更に本実施例では回路機能を拡大することがで
きる。
Example 2. FIG. 2 is a layout diagram showing a pattern layout of an IC chip according to another embodiment of the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. 1B is an IC chip, 5a,
5b are specific areas provided in the IC chip 1B, in which elements intended for a specific circuit configuration are arranged, similar to the specific area 5 in FIG. Here, it is assumed that the specific areas 5a and 5b have the same circuit function. In this way, in this embodiment, a plurality of specific regions 5a and 5b are provided in which elements having a specific circuit configuration are arranged in advance in the IC chip, so that the same effects as in the first embodiment can be obtained. In addition to this, the circuit function can be expanded in this embodiment.

【0014】実施例3.図3はこの発明の更に他の実施
例によるICチップのパターンレイアウトを示す配置図
である。図3において、図2に対応する部分には同一符
号を付し、その説明を省略する。1CはICチップ、5
c,5dは特定の回路構成を目的とする素子を配置した
特定領域である。なお、ここでは、特定領域5c,5d
は同一の回路機能を有するが、特定領域5a,5bとは
異なる回路機能を有するものとする。このように、本実
施例では、ICチップ内に予め特定の回路構成を想定し
た各素子を配置した特定領域5a,5bと5c,5dを
設け、特定領域5a,5bと特定領域5c,5dの回路
機能を異なるようにしたので、上記実施例1と同様の作
用効果が得られると共に更に本実施例では複雑な回路機
能が可能となり、より一層全体の回路機能を拡大できる
Example 3. FIG. 3 is a layout diagram showing a pattern layout of an IC chip according to still another embodiment of the present invention. In FIG. 3, parts corresponding to those in FIG. 2 are designated by the same reference numerals, and their explanations will be omitted. 1C is an IC chip, 5
c and 5d are specific areas in which elements intended for a specific circuit configuration are arranged. Note that here, specific areas 5c and 5d
have the same circuit function, but have a different circuit function from the specific areas 5a and 5b. As described above, in this embodiment, specific areas 5a, 5b and 5c, 5d are provided in the IC chip, in which elements having a specific circuit configuration are arranged in advance, and specific areas 5a, 5b and specific areas 5c, 5d are arranged. Since the circuit functions are made different, the same effects as in the first embodiment can be obtained, and this embodiment also allows complex circuit functions, thereby further expanding the overall circuit function.

【0015】[0015]

【発明の効果】以上のように、この発明によれば、IC
チップ内に特定の回路構成を目的とする素子を配置した
特定領域を備えたので、パターンレイアウトが簡単とな
り、しかも電気的特性を向上できるという効果を奏する
[Effects of the Invention] As described above, according to the present invention, the IC
Since the chip includes a specific area in which elements intended for a specific circuit configuration are arranged, pattern layout is simplified and electrical characteristics can be improved.

【0016】また、この発明によれば、ICチップ内に
特定領域を複数個備えたので、パターンレイアウトが簡
単で、電気的特性を向上できると共に回路機能を拡大で
きるという効果を奏する。
Further, according to the present invention, since a plurality of specific areas are provided within an IC chip, the pattern layout is simple, electrical characteristics can be improved, and circuit functions can be expanded.

【0017】また、この発明によれば、ICチップ内に
回路機能の異なる特定の領域を複数個備えたので、パタ
ーンレイアウトが簡単で、電気的特性を向上できると共
に複雑に回路機能が可能となり、更に全体の回路機能を
拡大できるという効果を奏する。
Further, according to the present invention, since a plurality of specific areas with different circuit functions are provided in the IC chip, the pattern layout is simple, electrical characteristics can be improved, and complex circuit functions are possible. Furthermore, there is an effect that the overall circuit function can be expanded.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】この発明の一実施例を示す配置図である。FIG. 1 is a layout diagram showing an embodiment of the present invention.

【図2】この発明の他の実施例を示す配置図である。FIG. 2 is a layout diagram showing another embodiment of the invention.

【図3】この発明の更に他の実施例を示す配置図である
FIG. 3 is a layout diagram showing still another embodiment of the present invention.

【図4】従来のアナログアレイを示す配置図である。FIG. 4 is a layout diagram showing a conventional analog array.

【符号の説明】[Explanation of symbols]

1A,1B,1C    ICチップ 2a〜2d,2i    抵抗器 3a〜3d,3i〜3m    トランジスタ4a〜4
d    アルミ配線 5,5a〜5d    特定領域
1A, 1B, 1C IC chips 2a to 2d, 2i Resistors 3a to 3d, 3i to 3m Transistors 4a to 4
d Aluminum wiring 5, 5a to 5d specific area

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  ICチップ内に特定の回路構成を目的
とする素子を配置した特定領域を備えたことを特徴とす
るアナログアレイ。
1. An analog array characterized in that an IC chip includes a specific area in which elements intended for a specific circuit configuration are arranged.
【請求項2】  ICチップ内に特定領域を複数個備え
た請求項1記載のアナログアレイ。
2. The analog array according to claim 1, further comprising a plurality of specific areas within an IC chip.
【請求項3】  ICチップ内に回路機能の異なる特定
の領域を複数個備えた請求項1記載のアナログアレイ。
3. The analog array according to claim 1, wherein the IC chip includes a plurality of specific areas having different circuit functions.
JP14197791A 1991-06-13 1991-06-13 Analog array Pending JPH04365367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14197791A JPH04365367A (en) 1991-06-13 1991-06-13 Analog array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14197791A JPH04365367A (en) 1991-06-13 1991-06-13 Analog array

Publications (1)

Publication Number Publication Date
JPH04365367A true JPH04365367A (en) 1992-12-17

Family

ID=15304528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14197791A Pending JPH04365367A (en) 1991-06-13 1991-06-13 Analog array

Country Status (1)

Country Link
JP (1) JPH04365367A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194640A (en) * 1986-02-20 1987-08-27 Fujitsu Ltd Semiconductor integrated circuit using bump mounting
JPH01244641A (en) * 1988-03-25 1989-09-29 Fujitsu Ltd Semiconductor integrated circuit
JPH01248535A (en) * 1988-03-29 1989-10-04 Nec Corp Semi-custom integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62194640A (en) * 1986-02-20 1987-08-27 Fujitsu Ltd Semiconductor integrated circuit using bump mounting
JPH01244641A (en) * 1988-03-25 1989-09-29 Fujitsu Ltd Semiconductor integrated circuit
JPH01248535A (en) * 1988-03-29 1989-10-04 Nec Corp Semi-custom integrated circuit

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