JPS595657A - Master slice system semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To select several gate power by previously forming a plurality of resistance patterns in a diffusion process. CONSTITUTION:When a wiring 5 is brought into contact with a window 2 and a wiring 6 is brought into contact with a window 3, a resistance value obtained is 2.RC of diffusion resistor 1 itself. When the wiring 5 is extended up to a window 4, on the other hand, a resistance value obtained is half the diffusion resistor 1, RC. When the wiring 6 is brought into contact with the window 4 at a central section and the wiring 5 is brought into contact with the windows 2, 3 at both ends, the diffusion resistor 1 functions as a parallel resistor turned up at the central section, and a resistance value obtained is RC/2. A wiring 21 is connected to windows 17-19 in all cases, but a resistance value obtained is 2.RE only by a diffusion resistor 11 when a wiring 20 is connected only to a window 14. When the wiring 20 is connected to windows 14, 15 and diffusion resistors 11, 12 are used in parallel, on the other hand, a resistance value obtained is RE. When diffusion resistors 11-13 are used in parallel, a resistance value obtained is RC/2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a master slice type gate array semiconductor integrated circuit, and in particular to a device that allows power changes of internal gates to be easily performed.

Conventional technology and problems Master slice LS in which elements necessary for a large number of gates are formed on a semiconductor substrate in advance, leaving only the final wiring process.
In I, there is no room to select the power of the internal gate in the final wiring process. For this reason, it is not possible to select in the final wiring process, such as increasing the gate power used in parts where the circuit operation speed is high and reducing the gate power used in parts where the speed can be slow. FIG. 1 shows an example of this type of internal gate, which is a constant current type ECL (emitter-coupled logic). Ql, Q2
is a transistor constituting a current switch, Q3 is a transistor for a constant current source, and Q g .

Q5 is an output stage transistor connected as an emitter follower. The power of this gate is the transistor Q41 Q
i, emitter resistance REF of Q3, current IE flowing through RE
F, IE% especially the emitter resistance RE of transistor Q3
It is determined by the constant current rE flowing through.

The current 1gr is determined by the value of the resistor REF, and the current 8
are the collector side resistance Rc and the emitter side resistance R.

The resistance ratio RC/RE is determined by the value of the output amplitude (
VOL), so normally the IE is determined by changing Re and RE so that RC/RE does not change. However, in the conventional master slicing method, the values of these resistances (diffused resistances) REF, RC, and REO are uniquely determined by the diffusion process, so the power of each gate cannot be changed in the final wiring.

OBJECTS OF THE INVENTION The present invention attempts to make it possible to select individual gate powers by forming a plurality of resistance patterns in advance through a diffusion process.

Structure of the Invention The present invention provides a master slice in which elements necessary for arrays of a large number of external and internal gates are formed in advance on a semiconductor substrate, and the elements are connected in the final wiring process to form a required circuit. In this type of semiconductor integrated circuit, the resistance element that determines the power of the internal gate is a single diffused resistor with a contact window for an intermediate tap, or a mutual The present invention is characterized by forming two or more independent diffused resistors provided with connection contact windows, which will be described in detail below with reference to the illustrated embodiments.

Embodiment of the Invention FIGS. 2 and 3 are planar patterns showing an embodiment of the invention. Figure 2 relates to the collector resistor Rc in Figure 1, where l is a diffused resistor formed to have a total length of 2·Rc, and 2 to 4 are provided at both ends and in the center of the resistor. A window for contact, 5 is an aluminum (Al) wiring on the earth GND side, and 6 is an AJ wiring on the collector side. (In the example of al, the wiring 5 is in contact with the window 2, and the wiring 6 is in contact with the window 3, so the obtained resistance value is 2·Rc of the diffused resistor 1 itself. In contrast, bl is the wiring 5 is extended to window 4, the resulting resistance value is half of the diffused resistance l, or Rc.

(Since C1 contacts the wiring 6 with the window 4 at the center, and the wiring 5 contacts the windows 2 and 3 at both ends, the diffused resistance l functions as a parallel resistance folded back at the center,
The resulting resistance value is Re/2.

Figure 3 relates to the emitter resistor RE, 11 to 13.
are three diffused resistors each having a resistance value of 2 RE, 1
4 to 16 and 17 to 19 are contact windows at both ends;
0 is an Al wiring connected to the emitter side of the transistor Q3, and 21 is an Al wiring on the negative power supply VEE side. In all cases, wire 21 is connected to windows 17-19, but (8
), wiring 2o is only connected to window 14, so
The resistance value obtained is 2.RE, which depends only on the diffused resistor 11. On the other hand, in b), the wiring 2o is connected to the window 14.15 and the diffused resistor 11.12 is used in parallel, so the obtained resistance value is R, and (C1 is the diffused resistor 11.12).
~13 are used in parallel, so the obtained resistance value is Re
/2.

Considering the combination of Fig. 2(b) and Fig. 3(b) as standard, when increasing the collector resistance and reducing the gate power as shown in Fig. 2(al), the emitter side is Figure 3 (
By making it like al, the resistance ratio RC/RE can be kept constant. Also, as shown in Figure 2 +c+, when increasing the gate power by decreasing the collector resistance, the emitter side is
The resistance ratio Rc/O can be kept constant by making it as shown in Figure (C1).In this way, the resistance width (value) on the emitter side
This change is essential for correcting the VBg fluctuation of transistor Q3 due to changes in current IE. This allows the output level to remain unchanged even if the power is changed. still,
The collector resistance can also be realized by using two diffused resistors, each with a resistance value Rc, but this is not done in order to avoid changing the parasitic capacitance of the resistors and affecting the switching speed. That is, (a
l and (C1 both use the entire diffused resistor 1,
(Originally, only half of bl is required. Therefore, when using two diffused resistors, (al, (0) is 2, (bl is 1)
Since it is a book, the parasitic capacitance of Ta) and (e) is l
It will be twice as much as b). In this example, to avoid this, (b)
The wiring 5 is brought into contact with the window 2 in addition to the originally necessary window 4, thereby making the parasitic capacitance equal to Ta) (c+).

Effects of the Invention As described above, according to the present invention, it is possible to give selectivity to the internal gate power in the final wiring process in a gate array type master slice LSI, so that there is an advantage that optimum power distribution is possible. be.

[Brief explanation of drawings]

Figure 1 shows E used as an internal gate of a gate array.
The equivalent circuit diagram of the CL gate, FIGS. 2 and 3 are plane pattern diagrams showing one embodiment of the present invention. In the figure, 1.11-13 are diffused resistors, 2-4 are contact windows, and 5. 6. 20. 21 is an Al wiring. Applicant Fujitsu Limited Representative Patent Attorney Minoru Aoyagi

Claims (1)

[Claims] In a master slice type semiconductor integrated circuit, in which elements necessary for arrays of a large number of external and internal gates are formed in advance on a semiconductor substrate, and the required circuits are constructed by connecting the elements in the final wiring process, As the resistance element that determines the power of the internal gate, one diffused resistor is provided with a contact window for an intermediate tap, or a contact window is provided for interconnection, so that two or more resistance values can be selected. A master slice type semiconductor integrated circuit characterized by forming two or more independent diffused resistors.