JPS6237538B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor fixed memory device, and particularly to the structure of a memory cell of a junction-destructive programmable read-only memory (PROM).

In the conventional junction breakdown type PROM memory cell, one collector is pulled up every four to eight cells, as shown in FIGS. 1 and 2. To explain the figures, FIG. 1 shows a circuit diagram thereof, and FIG. 2 shows a transistor pattern on the surface of a semiconductor substrate. Reference numeral 2 denotes a collector region provided on the semiconductor substrate surface 1, in which collector electrodes 3,
4 is provided. Collector electrodes 3 and 4 are connected to word line W. Collector area 2
A plurality of base regions 5 to 8 are provided independently, and emitter regions 9 to 12 are provided within each base region. As a method for forming the base region and emitter region, a selective impurity diffusion method known in the field of semiconductor device manufacturing is used. Furthermore, the surfaces of each of the collector region, base region, and emitter region are covered with an insulating thin film such as an SiO ₂ film, except for necessary electrode regions. Reference numerals 13 to 16 are connected only to the emitter by an electrode layer provided after opening a hole in the SiO ₂ film on the emitter region, and each acts as a bit line.

Now, when writing desired information into the memory cell of the PROM shown in FIG. 2, a write current is applied to any one of _B1 to _B4 . For example, when a write current is applied to 14 (B ₂ ) in FIG. 2, the PN junction (reverse biased) between the base region 6 and the emitter is destroyed and fixed in a conductive state.

Now, the write current is applied to the memory cell of the conventional PROM shown in FIG.
(B ₂ ), the current branches as shown by arrows 17 and 18. This means that the write current is dispersed, the current concentration is reduced, and a larger current needs to flow to cause junction breakdown. On the other hand, the write current is applied to the endmost electrode layer,
For example, when flowing through the electrode 13 (B ₁ ), most of the current flows in the direction of the collector electrode 3, so the current concentration is good, and even a low current can cause junction breakdown.

In this way, conventional PROM memory cells
There is a variation of about 20 to 30% in the write current value,
There was a drawback that the overall write current had to be increased in order to prevent write failures.
This requires a large capacity peripheral circuit element, leading to an unbalance in area between the memory cell and the peripheral circuit portion, and also causing a decrease in the degree of integration of the PROM.

Therefore, the purpose of the present invention is to propose a PROM memory cell that can reduce the variation in write current value, lower the write current value as a whole, reduce the area of peripheral circuits, and increase the degree of integration. be.

The present invention solves the drawbacks of conventional memory cells in that a plurality of collector electrodes are provided in the collector region 2 (FIG. 2), and the write current is shunted to each collector electrode. Focusing on this problem, the memory of the present invention divides the collector region into a plurality of regions, provides a collector electrode in each collector region, and has one collector electrode in one collector region. The memory cell is characterized in that it is composed of a memory cell in which a pair of base region and emitter region are arranged symmetrically with respect to one collector electrode so that only current flows therethrough.

In the memory cell of the present invention, the write current flows only in a fixed direction in each cell, and the current concentration is high.
Writing becomes extremely easy.

In particular, since the variation in write current is extremely small, the write current value can be lowered, and the peripheral circuitry can also be made smaller in proportion. As a result, the degree of integration of the PROM as a whole can be increased.

3 and 4 are diagrams for explaining an embodiment of the present invention, where FIG. 3 is a circuit diagram and FIG. 4 is a diagram looking at the surface of a semiconductor substrate. FIG. 3 shows exactly the same circuit as FIG. 1. In the figure, the same reference numerals as in FIGS. 1 and 2 indicate the same parts.

The obvious difference between FIG. 4 and FIG. 2 is that the collector area 2 in FIG.
0, collector electrodes 21 and 22 are provided in each of the divided collector regions, and a base region and an emitter region are provided symmetrically on both sides of the collector electrode. A memory cell having such a structure can be easily realized by using microfabrication techniques such as impurity diffusion photoresist processing known in the field of semiconductor device manufacturing.

In the cell shown in FIG. 4, the write current flows as shown by arrows 23, 24, 25, and 26, and is in a constant direction in each cell. As a result, in the results of the examples of the present invention, it was possible to reduce the write current by 20 to 30% compared to the conventional cell (shown in FIG. 2).

[Brief explanation of the drawing]

1 and 3 are circuit diagrams of a memory cell of a junction breakdown type PROM, and FIG. 2 is a surface diagram of a conventional semiconductor substrate when the circuit of FIG. 1 is configured into a semiconductor integrated circuit.
FIG. 4 is a surface view of a semiconductor substrate of a memory cell according to the present invention. 1... Semiconductor substrate surface, 5-8... Base region, 9-12... Emitter region, 13-16...
Electrode layer, 19, 20... Collector region, 21, 2
2...Collector electrode.

Claims (1)

[Claims] 1. In a junction-destructive programmable memory comprising memory cells formed in each of a plurality of common collector regions divided into a semiconductor substrate, the memory cell has one collector electrode connected to a part of the common collector region. a pair of base regions sandwiching the collector electrode and arranged symmetrically in the common collector region with respect to the collector electrode; and a pair of base regions respectively formed in the pair of base regions and arranged symmetrically with respect to the collector electrode. The pair of emitter regions of the memory cell are respectively connected to different write current supply lines, and a write current is supplied to the selected write current supply line through the one collector electrode. A junction-destructive programmable memory characterized in that it is formed so as to be supplied.