JPS6220367A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To contrive reducing the plane dimensions of a memory cell and improving the degree of integration by making the memory cell by selectively introducing or not introducing a reverse conductive type impurity in a polycrystalline silicon layer. CONSTITUTION:An interlayer insulation film 6 is formed on a polycrystalline insulation film 6 and an aluminum wiring 8 laid in parallel with the drawing on the interlayer insulation film 6 is connected for conduction to the polycrstalline silicon layer 5 through the contact hole 7. Word wires W1-W3 are made with a polycrystalline silicon layer 3 and a metal silicide layer 4, data wires D1, D2 are made with the aluminum wiring 8 and a memory cell is made at the crossing of both the wires. The memory cell is made with a diode of P-N junction formed by selectively introducing a reverse conductive type impurity or a high resistance which is not introduced with the reverse conductive type impurity. This enables reducing the plane dimensions of the memory cell, miniaturizing the cell and achieving the high degree of integration of the cell.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device suitable for application to a mask ROM.

[Background technology]

Generally, mask ROM is a bipolar transistor or MO3
By forming type transistors as memory cells and making the characteristics and electrical connections of these cells different from those of other cells, so-called rewriting (writing) of information is performed. However, in this type of mask ROM, since there is a limit to the reduction in the planar dimensions of each cell, it is difficult to miniaturize the cells, that is, to improve the degree of integration. Also, a memory device in which the memory cell is constructed with a diode instead of a transistor has been proposed, but since the diode is constructed with an impurity layer formed on the main surface of the semiconductor substrate, it is difficult to reduce the planar dimensions. Similarly, there are limitations and it is difficult to significantly increase the degree of integration.

The mask ROM is described, for example, in Nyoi Shoten, Integrated Circuit Application Handbook, published June 30, 1981, page 384 onwards.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device in which the degree of integration can be improved by miniaturizing a mask ROM in which memory cells are composed of diodes.

The above and other objects and novel features of the present invention include:
It will be clear from the description of this specification and the accompanying drawings that δ is the same.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a word line is constituted by a conductivity type layer extended on an insulating film and a silicide layer provided thereon, and a polycrystalline silicon layer is formed on this silicide layer.
Furthermore, a data line is formed by wiring extending in a perpendicular direction through an insulating film, and an impurity of an opposite conductivity type is selectively introduced into the polycrystalline silicon layer at the intersection thereof, or is not introduced. By configuring the memory cell, the planar dimensions of the memory cell can be reduced and a semiconductor memory device with a high degree of integration can be obtained.

〔Example〕

1 and 2 are a plan view and a sectional view taken along the line AA of an embodiment of the present invention. As shown in the figure, a thick insulating film 2 such as a silicon oxide film is formed on the main surface of a semiconductor substrate 1 made of silicon, etc.
A polycrystalline silicon layer 3 containing impurities is extended. Further, on the upper surface of this polycrystalline silicon layer 3, a metal silicide layer 4 made of silicided metal such as molybdenum is formed.
are integrally formed. Further, a polycrystalline silicon layer 5 is formed overlying this metal silicide layer 4.

An impurity of the opposite conductivity type (P type) is selectively introduced into this polycrystalline silicon layer 5, and at the place where the opposite conductivity type is introduced, a PN junction is formed with the N type layer below. It forms a diode, and forms a high resistance in areas where impurities are not introduced.

A glabellar insulating film 6 is formed on the polycrystalline silicon layer 5, a contact hole 7 is formed in the glabellar insulating film 6, and an aluminum wiring 8 is formed on the interlayer insulating film 6 in parallel with the plane of the paper. It is electrically connected to the polycrystalline silicon layer 5 through a contact hole 7.

With this configuration, as shown in FIG. 3, the polycrystalline silicon layer 3 and the metal silicide layer 4 are connected to the word lines w, , w2 . W, and the aluminum wiring #as
data lines DI and Di are formed, and memory cells are formed at the intersections of these two lines. This memory cell has a configuration of either a diode made of a PN junction formed by selectively introducing impurities of the opposite conductivity type, or a high resistance structure in which impurities of the opposite conductivity type are not introduced. .

FIGS. 2A to 2C show a method of manufacturing the semiconductor memory device.

First, as shown in the same figure (A), lii! on the silicon base triil! A polycrystalline silicon layer 3 doped with an N-type impurity such as phosphorus is formed on the I edge film 2, and a metal film such as molybdenum is deposited thereon and then heat treated to form a molyb silicide layer 4. Moreover, a polycrystalline silicon layer 5 into which no impurity is introduced is formed on this.

Next, as shown in the same figure (E), the polycrystalline silicon layer 3
, the molyb silicide layer 4 and the polycrystalline silicon layer 5 are patterned into strips and ribs in a direction perpendicular to the plane of the paper by a well-known photolithography technique, and an interlayer insulating film 6 such as PSG is formed thereon.

As shown in the same figure (C), this interlayer insulating film 6 has
Contact holes 7 are formed on the polycrystalline silicon layer 5 at equal pitch intervals. Then, a photoresist 9 is formed and patterned to expose the desired contact hole 7, and using this photoresist 9 as a mask, a P-type impurity such as poron is added to the polycrystalline silicon corresponding to the contact hole 7. Introduced into layer 5 part. As a result, a PN junction is formed in this contact hole portion, and a high resistance is formed in other portions.

Next, the frame I resist 9 is removed, aluminum is deflamed and deposited, and then patterned in the direction H parallel to the bald paper surface to form the aluminum wiring 8, the second structure can be obtained.

(In order to write information, first select one of the data lines I while precharging all the word lines W.). After that, one word line is selected and discharged, the memory cell is redundantly selected, and the memory cell corresponding to this memory cell is discharged.
The potential of the evening light is detected by a sense amplifier. If type 1) impurities are introduced into the polycrystalline silicon layer 5 in the selected memory cell, the charge on the data line flows through the diode of the memory cell and the potential becomes low, and conversely the polycrystalline silicon When the layer 5 has a high resistance, the charge on the data line does not flow, so the potential becomes high level.

From this Ql:, it is possible to read out the state of the information formula Δ (z) of the corresponding memory cell.

According to this semiconductor memory device C, the memory cell is formed at the intersection of the polycrystalline silicon layer 3, the metal silicide layer 4, and the polycrystalline silicon layer 5 with the aluminum wiring 8. It is possible to achieve miniaturization and high integration of memory cells. In addition, the word line is formed on a thick insulating film and the capacitance (4JI) is always kept small by 2σ), which speeds up the precharge and discharge time. Readout can be done in real life.

〔effect〕

(1) Since the memory cell is made of aluminum in the underlying polycrystalline silicon layer, metal silicide layer, and polycrystalline 99777 layer, there is no need to form an impurity layer on the semi-quadratic substrate, and the planar dimensions of the memory cell can be reduced. It is possible to miniaturize cells and achieve high cell integration.

(2) The polycrystalline silicon layer, etc. that make up the word line of the memory cell is constructed with thick insulation.

It is possible to improve the charging speed by reducing the capacitance of the word line, and it is also possible to increase the reading speed by reducing the capacitance of the data line.

(3) Metal pattern on the polycrystalline silicon layer as a word line
1. Since the lizard layer 4 is formed. By lowering the resistance of the word line, it is possible to prevent the m-type impurity on the polycrystalline silicon layer from diffusing into the polycrystalline silicon layer on the + side, reducing the high resistance of the memory cell. The state can be maintained.

(4) Writing to the memory cell can be done simply by selectively adding impurities of the opposite conductivity type, so that +W information can be written quickly.

Hereinafter, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to -1-input flow side, and various changes may be made without departing from the gist thereof. Needless to say, it is possible to introduce a P-type impurity into the lower polycrystalline silicon layer constituting the word line, and selectively introduce it into the polycrystalline silicon layer on the second side. An N-type impurity may be used as the impurity.

Furthermore, the impurity layer serving as the word line 7 may be made of a material such as polycrystalline silicon.

[Application field]

In the above explanation, we will mainly explain the case where the invention made by the inventor of the invention was applied to mask ROM, which is the background of the invention. It can also be applied to microcomputers, etc.

[Brief explanation of drawings]

Fig. 1 is a plan view of the - section of the embodiment of the present invention, Fig. 2 is a sectional view taken along line AA in Fig. 1, Fig. 3 is its equivalent circuit diagram, and Figs. 4 (A) to (C). FIG. 2 is a process cross-sectional view for explaining the manufacturing process. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Insulating film, 3... Polycrystalline silicon layer, 4... Metal silicide layer, 5... Polycrystalline silicon layer, 6... Interlayer insulating film, 7... ...Contact ball, 8...Aluminum wiring, 9...FoI resist. Figure 1 Figure 2 Figure 14 Kaisho 62-20367 (4) Figure 4 (A')

Claims (1)

[Claims] 1. A word line is constituted by a conductivity type layer extended on an insulating film and a silicide layer provided thereon, and a polycrystalline silicon layer is formed on the silicide layer, Furthermore, a data line is formed by wiring extending in a perpendicular direction through an insulating film, and an impurity of an opposite conductivity type is selectively applied to the polycrystalline silicon layer at the intersection of the word line and the data line. What is claimed is: 1. A semiconductor memory device characterized in that a memory cell is configured by introducing a semiconductor memory cell. 2. The semiconductor memory device according to claim 1, wherein the first conductivity type layer is a polycrystalline silicon layer into which one conductivity type impurity is introduced. 3. A contact hole is formed in the insulating film at the intersection with the data line, and an impurity of the opposite conductivity type is introduced into the polycrystalline silicon layer through the exposed contact hole using a photoresist as a mask. 2. The semiconductor memory device according to item 2.