JPS6480069A - Semiconductor storage device and manufacture thereof - Google Patents

Semiconductor storage device and manufacture thereof

Info

Publication number
JPS6480069A
JPS6480069A JP23481787A JP23481787A JPS6480069A JP S6480069 A JPS6480069 A JP S6480069A JP 23481787 A JP23481787 A JP 23481787A JP 23481787 A JP23481787 A JP 23481787A JP S6480069 A JPS6480069 A JP S6480069A
Authority
JP
Japan
Prior art keywords
type
data
write
cells
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23481787A
Other languages
Japanese (ja)
Other versions
JP2820152B2 (en
Inventor
Isamu Kobayashi
Takashi Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP23481787A priority Critical patent/JP2820152B2/en
Publication of JPS6480069A publication Critical patent/JPS6480069A/en
Application granted granted Critical
Publication of JP2820152B2 publication Critical patent/JP2820152B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To cut down the time required for completion of a vertical ROM by a method wherein, after previously composing all memory cells in depletion type, selected cells are changed into enhancement type etc., to write data therein. CONSTITUTION:Overall surface of the active region of a semiconductor substrate 1 is channel-doped with n-type impurity to form N<->type layer 4 thus data 1 are written in all cells of a memorial array. Later, word lines W1-W3, source, drain region 5 comprising a gate electrode are formed to form a depletion type MISFET. Then, after forming an interlayer insulating film 6 and a data line 7, a channel part of memory cell to write the data 1 therein e.g. FETQ2 is doped with p type impurity to change the n-type of said impurity layer 4 into a p-type impurity layer 9. Through these procedures, after forming the data line 7 etc., the channel part can be composed in enhancement type or mild depletion type to write the data 1 therein so that the turnaround time required for the completion of ROM may be cut down.
JP23481787A 1987-09-21 1987-09-21 Method for manufacturing semiconductor memory device Expired - Fee Related JP2820152B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23481787A JP2820152B2 (en) 1987-09-21 1987-09-21 Method for manufacturing semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23481787A JP2820152B2 (en) 1987-09-21 1987-09-21 Method for manufacturing semiconductor memory device

Publications (2)

Publication Number Publication Date
JPS6480069A true JPS6480069A (en) 1989-03-24
JP2820152B2 JP2820152B2 (en) 1998-11-05

Family

ID=16976849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23481787A Expired - Fee Related JP2820152B2 (en) 1987-09-21 1987-09-21 Method for manufacturing semiconductor memory device

Country Status (1)

Country Link
JP (1) JP2820152B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423358A (en) * 1990-05-14 1992-01-27 Matsushita Electron Corp Manufacture of semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150860A (en) * 1980-04-24 1981-11-21 Fujitsu Ltd Manufacture of semiconductor memory device
JPS5856468A (en) * 1981-09-30 1983-04-04 Fujitsu Ltd Manufacture of semiconductor
JPS58111364A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Manufacture of read-only memory
JPS6020562A (en) * 1983-07-14 1985-02-01 Toshiba Corp Mos semiconductor device and manufacture thereof
JPS6220367A (en) * 1985-07-19 1987-01-28 Hitachi Ltd Semiconductor memory
JPS6246556A (en) * 1985-08-26 1987-02-28 Hitachi Ltd Semiconductor memory device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150860A (en) * 1980-04-24 1981-11-21 Fujitsu Ltd Manufacture of semiconductor memory device
JPS5856468A (en) * 1981-09-30 1983-04-04 Fujitsu Ltd Manufacture of semiconductor
JPS58111364A (en) * 1981-12-25 1983-07-02 Hitachi Ltd Manufacture of read-only memory
JPS6020562A (en) * 1983-07-14 1985-02-01 Toshiba Corp Mos semiconductor device and manufacture thereof
JPS6220367A (en) * 1985-07-19 1987-01-28 Hitachi Ltd Semiconductor memory
JPS6246556A (en) * 1985-08-26 1987-02-28 Hitachi Ltd Semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0423358A (en) * 1990-05-14 1992-01-27 Matsushita Electron Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JP2820152B2 (en) 1998-11-05

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees