JPS6433961A - Mos composite memory device - Google Patents

Abstract

PURPOSE:To enable a function as a nonvolatile RAM to be obtained in a small occupied area, by forming a memory cell which consists of substantial three transistors including a nonvolatile MOS transistor memory with a floating gate and one capacitor element in one semiconductor substrate. CONSTITUTION:A memory cell comprises a DRAM section including a first MOS transistor MT1 which is connected to a capacitor C, a nonvolatile memory section MT2 with a floating gate FG which is connected to the DRAM section, and a second MOS transistor MT3 which is connected to the nonvolatile memory section MT2. And, the DRAM section, the nonvolatile memory section MT2 and the second MOS transistor MT3 are formed together in the same semiconductor substrate. For example, a gate electrode 15 is formed over between a drain area 12 and a diffusion area 13 through a gate oxide film to the transistor MT1 for selecting element. And, an electrode 16 for forming the capacitor C is superposed on the diffusion area 13 through the oxide film, and a floating gate 17 is so formed as to have an insulating film section A with very thin thickness for writing and erasing over a part of the diffusion area 13; moreover, a control gate 18 is formed over the floating gate 17.