JPS5791561A - Semiconductor non-volatile memory device and manufacture therefor - Google Patents

Semiconductor non-volatile memory device and manufacture therefor

Info

Publication number
JPS5791561A
JPS5791561A JP16749080A JP16749080A JPS5791561A JP S5791561 A JPS5791561 A JP S5791561A JP 16749080 A JP16749080 A JP 16749080A JP 16749080 A JP16749080 A JP 16749080A JP S5791561 A JPS5791561 A JP S5791561A
Authority
JP
Japan
Prior art keywords
region
gate
selecting
memory device
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16749080A
Other languages
Japanese (ja)
Inventor
Shinpei Tsuchiya
Takashi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16749080A priority Critical patent/JPS5791561A/en
Publication of JPS5791561A publication Critical patent/JPS5791561A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase integration and to reduce erase/write voltage by a method wherein a control gate and a floating gate are extended on a selecting Tr and a thin film section shallower than the diffusion depth at a D region is provided at the end section of a gate insulating film. CONSTITUTION:A selecting gate 20, a first gate oxide film 19, and an N<+> type D region 12 are formed on a P type substrate 1 and a selecting transistor is formed at an S region 13, and the region 13 also consists of an S region 14, a second gate oxide film 17, a floating gate 15, and a control gate 16 at the D region of a memory transistor to unitedly form a memory Tr and a selecting Tr. The floating gate 15 and the control gate 16 extend on the selecting gate 20 and the second gate insulating film 17 becomes a thin film section 18 with 200Angstrom or below around the D region 13 to form a thickness shallower than the diffusion depth of the D region. In this way, erase/write voltage can be reduced without losing integration.
JP16749080A 1980-11-28 1980-11-28 Semiconductor non-volatile memory device and manufacture therefor Pending JPS5791561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16749080A JPS5791561A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory device and manufacture therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16749080A JPS5791561A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory device and manufacture therefor

Publications (1)

Publication Number Publication Date
JPS5791561A true JPS5791561A (en) 1982-06-07

Family

ID=15850639

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16749080A Pending JPS5791561A (en) 1980-11-28 1980-11-28 Semiconductor non-volatile memory device and manufacture therefor

Country Status (1)

Country Link
JP (1) JPS5791561A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4589009A (en) * 1984-10-09 1986-05-13 The United States Of America As Represented By The Secretary Of The Army Non-volatile piezoelectric memory transistor
US4861730A (en) * 1988-01-25 1989-08-29 Catalyst Semiconductor, Inc. Process for making a high density split gate nonvolatile memory cell
US4989054A (en) * 1988-08-26 1991-01-29 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device using contact hole connection
US5049516A (en) * 1987-12-02 1991-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor memory device
EP0535694A2 (en) * 1991-10-03 1993-04-07 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US5253196A (en) * 1991-01-09 1993-10-12 The United States Of America As Represented By The Secretary Of The Navy MOS analog memory with injection capacitors
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
EP1313148A2 (en) * 1997-01-31 2003-05-21 Integrated Memory Technologies, Inc. A scalable flash eeprom memory cell, method of manufacturing and operation thereof
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4589009A (en) * 1984-10-09 1986-05-13 The United States Of America As Represented By The Secretary Of The Army Non-volatile piezoelectric memory transistor
US5049516A (en) * 1987-12-02 1991-09-17 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor memory device
US4861730A (en) * 1988-01-25 1989-08-29 Catalyst Semiconductor, Inc. Process for making a high density split gate nonvolatile memory cell
US4989054A (en) * 1988-08-26 1991-01-29 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device using contact hole connection
US5100818A (en) * 1988-08-26 1992-03-31 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor memory device and method of manufacturing the same
US5514607A (en) * 1991-01-03 1996-05-07 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor memory device
US5253196A (en) * 1991-01-09 1993-10-12 The United States Of America As Represented By The Secretary Of The Navy MOS analog memory with injection capacitors
US5359218A (en) * 1991-10-03 1994-10-25 Kabushiki Kaisha Toshiba Semiconductor memory device with selection gate in a groove
EP0535694A2 (en) * 1991-10-03 1993-04-07 Kabushiki Kaisha Toshiba Semiconductor memory device and method of manufacturing the same
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6057575A (en) * 1996-03-18 2000-05-02 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell, method of manufacturing and operation thereof
EP1313148A2 (en) * 1997-01-31 2003-05-21 Integrated Memory Technologies, Inc. A scalable flash eeprom memory cell, method of manufacturing and operation thereof
EP1313148A3 (en) * 1997-01-31 2004-03-03 Integrated Memory Technologies, Inc. A scalable flash eeprom memory cell, method of manufacturing and operation thereof

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