JPS6020562A - Mos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten turn around time at an MOS type mask ROM by a method wherein after the polycrystalline silicon gate electrode films of the MOS type mask ROM are formed, ROM data are written without enlarging an accelerating voltage. CONSTITUTION:N type impurities, arsenic As ions for example, are implanted into a silicon substrate 21 at both the side regions of polycrystalline silicon gate electrodes 241, 242 to form N type layers 251-253 to be used as sources and drains, and cell transistors 26, 27 are formed. Then a resist film 29 having an opening 28 at the part of the electrode film 242 of the specified transistor 27 and in the neighboring region thereof is formed. P type impurities, boron ions B<+>11 for example, are implanted through the opening 28. Then after a CVD-SiO2 film 31 is formed, heat treatment is performed. Accordingly, the regions implanted with boron are diffused to be deeper than the regions implanted with arsenic As, and at the same time, diffused to be formed in the lateral direction toward the channel sides, and P<+> type layers 321, 322 are formed in the regions along the side parts of the channel sides from the under parts of the layers 252, 253. By forming the layers 321, 322 in such a way, ROM data can be written.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a MOS (Metal Oxide semiconductor)
onductor type semiconductor device and its manufacturing method, particularly MoS type mask ROM (manufacturing method).
This paper relates to improvements in data writing for memory (Memory).

[Technical background of the invention]

Conventionally, this type of ROM has been configured as shown in FIG. 1, for example. Here, data is written into one cell transistor 7 of the cell transistors J,2. In manufacturing this ROM, first, a P-type silicon substrate 11 is field oxidized to form a field oxide film 12.

Next, 'P E P (Photo box)
g Process), the cell transistor 24G
1! A P-type impurity, for example, poron B1□, is added to the channel region of l.
A P-type layer 13 is formed by ion implantation, and data 1: is written.

Next, after forming the gate oxide film 14, for example, CVD (CbLmicalVap) is applied on the gate oxide film 14.
A polycrystalline silicon film is deposited by our deposition method. Thereafter, polycrystalline silicon gate electrode films 151 and 152 are formed by PEP. Next, these polycrystalline silicon gates' acetic acid electrode films 15, . 1520 In the silicon substrate 11 on both sides, an N-type impurity such as arsenic A is added.
N-type layer Z that becomes the source and drain by ion-implanting s.
68,16□.

163 is formed. After that, CV is placed on the silicon substrate 11.
A D-8in2 film Z7i is formed. Next, Tono'CVD-
Contact hole 181°2 1 in S i O2 film 17
&s, and further these contact holes 18 to 18
Aluminum A/ is vapor-deposited on the third part to form electrode wiring 19□,
192.19. form.

As described above, in the conventional MOB type mask ROM, the polycrystalline silicon gate electrode film 15. .

By ion implantation before forming 15□! ROM data is written by changing the threshold value of a specific cell transistor Z.

[Problems with background technology]

By the way, in the mask ROM, the ROM is
It is required to shorten the production period (turnaround time) from receiving data to producing a product as much as possible. To this end, in the wafer manufacturing process,
It is desirable to write the ROIJ data in a later process.

However, in the conventional mask ROM manufacturing method, ions are implanted before forming the polycrystalline silicon gate electrode films 158 and 152 as described above, and RO'[ It is designed to write data.

For this reason, the above-mentioned turnaround time has become long. Note that after forming a polycrystalline silicon gate electrode, ions are implanted through this polycrystalline silicon gate electrode to change the threshold value of a specific cell/transistor, thereby making it necessary to increase the acceleration voltage for ion implantation. be. [1] For example, if the thickness of the polycrystalline silicon gate electrode film is 6000A or more, for example, boron B
,, When implanting k ions, the acceleration voltage is 160 K.
This becomes impossible below eV.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to:
To provide an MO8 type semiconductor device and its manufacturing method that can write ROU data without increasing the acceleration voltage after forming a polycrystalline silicon gate electrode film and shorten the turn around time. It's about doing.

[Machinery of invention]

After forming multiple cell transistors, the present invention uses polycrystalline silicon in a particular cell transistor.
[By ion-implanting an impurity with a conductivity type opposite to that of the source and drain J- diffusion impurities and having a large diffusion coefficient into the region near the pole, and forming a highly concentrated impurity layer in the channel region, a specific cell・Transistors and other cells・
The threshold value is set to be different from that of the transistor.

[Implementation sequence of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. First, as shown in FIG. 2(&), field oxidation is performed on, for example, a P-type silicon substrate 21 to form a field oxide film 22. As shown in FIG. Next, the gate oxide film 23 is removed by thermal oxidation, for example.
is formed and further arranged on this gate oxide film 23, CV
A polycrystalline silicon film is deposited by method D. After that, P
Perform EP and polycrystalline silicon gate electrode film 24. .

Form 24□. Next, these polycrystalline silicon gate electrode films 24. I 24. silicon substrate 21 on both sides of
N-type impurities such as arsenic As are ion-implanted into the N-type layers 25□, ,,25. form, and form cell t5 runcistary, L no. Next, as shown in FIG. 2(b), a resist film 29 having an opening 28 in the polycrystalline silicon gate electrode film 24□ of a specific transistor, for example, one cell transistor, and its vicinity is formed. Thereafter, P-type impurity ions, such as boron B, etc., are implanted through this opening 28. Here, these ions do not pass through the polycrystalline silicon gate electrode film 242, and as a result, the channel side partial region 30 of the N-type layers 25□, 253 on both sides of the polycrystalline silicon gate electrode film 242
1.30. Ions are implanted only in

Next, as shown in FIG. 21(C), a CVD-8i*2 film 3 is formed on the entire surface of the silicon substrate 21, and then heat treatment is performed. At this time, since the diffusion coefficient of boron B11 (approximately 1.0 × 10 -1 μ4 layer at a heat treatment temperature of 1050°C) is larger than the diffusion coefficient of arsenic As (approximately 4 × 10 μ/E at the same temperature), boron B11 The area where is implanted is arsenic As
It is diffused deeper than the implanted region, and at the same time is diffused laterally toward the channel side. As a result, an N-type layer 25□ becomes a source and a drain.

A P-type layer 321*322 is formed in a region along the channel side f%I (from the lower part of the CvD-8iO2 film 31, as in the conventional process). ..332.

33sf are provided respectively, and further, aluminum A/, for example, is vapor deposited in these contact holes 331 to 333 to form electrode wiring 34. 〜343 are formed. Furthermore, this electrode wiring 34. A protective film (not shown) is formed on ~348 to complete the mask ROIJ.

In the mask ROM manufactured in this way, P-type layers 321 and 322 extend from the source and drain sides to the channel region of a specific cell transistor, respectively, resulting in an impurity concentration in the channel region. is getting bigger. Therefore, the threshold values of the cell transistors 27 have different values. That is, P type layers 32, +32
2, it becomes possible to write ROIJ data. In addition, in order to write this ROM data, an impurity having a larger diffusion coefficient than the other impurities forming the source and drain is added to the polycrystalline silicon gate electrode film 2.
Since it is possible to implant the laser beam into the nearby area without passing through 42, there is no need to increase the acceleration voltage.

In the above embodiment, the P+ type layer 32. formed in the channel region of a specific cell transistor. ．． 32□ are respectively formed in a part of the channel region 7
However, the present invention is not limited to this, and the P type layer 32. ．．
P in the entire channel area so that 322 comrades are connected.
Of course, it is also possible to form a mold layer 1. [Effects of the Invention] As described above, according to the present invention, a polycrystalline silicon gate'
"By performing ion implantation after forming the electrode film,
Since the threshold value of a specific cell/transistor can be changed, ROM data can be written into the wafer at a later stage in the wafer fabrication process.
Around time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of a conventional IJO8 type O8 type mask R-; FIG. 2 is a sectional view showing the manufacturing process of an MO8 type mask ROM according to one embodiment of the present invention . 21...Silicon substrate, 22...Field oxide film, 23...Gate Fy, &oxide film, 24. ．． 242...
・Polycrystalline silicon gate'-: Polar film, 25 I+ 25
2 +253...N type 1g, 2 e l 2 y.
...Cell transistor, 32. ．． 322...P type layer.

Claims (1)

[Claims] [11M In an OS type mask ROM semiconductor device, in a region along the channel side from the bottom of each region of the source layer and drain layer of a specific cell transistor, An MO8 type semiconductor device characterized in that a highly concentrated impurity layer of a conductivity type opposite to that of the MO8 type semiconductor device is formed. +211+70 In a method of manufacturing an S-type mask ROM semiconductor device, a step of forming polycrystalline silicon gate electrodes in regions where cells and transistors are to be formed on a semiconductor substrate of a first conductivity type, and forming a polycrystalline silicon gate electrode on each of the polycrystalline silicon gate electrodes. a step of ion-implanting impurities of a second conductivity type into the semiconductor substrate on both sides to form a source layer and a drain layer to form a plurality of cell transistors; and a step of forming a plurality of cell transistors among the cell transistors. A first conductivity type impurity having a larger diffusion coefficient than the second conductivity type impurity is ion-implanted into a region near the polycrystalline silicon gate electrode in the source layer and the drain layer from the bottom of each region toward the channel side. forming a highly concentrated impurity layer in a region along the sides of the UO.
A method for manufacturing an S-type semiconductor device.