JPS6159750A - Semiconductor device and manufacture of the same - Google Patents
Semiconductor device and manufacture of the sameInfo
- Publication number
- JPS6159750A JPS6159750A JP18100484A JP18100484A JPS6159750A JP S6159750 A JPS6159750 A JP S6159750A JP 18100484 A JP18100484 A JP 18100484A JP 18100484 A JP18100484 A JP 18100484A JP S6159750 A JPS6159750 A JP S6159750A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- oxide film
- insulating layer
- region
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title description 7
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 238000001020 plasma etching Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000012856 packing Methods 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 description 8
- 238000001459 lithography Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、素子の高密度化を図ることを可能にした半導
体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, which make it possible to increase the density of elements.
従来、素子領域と配線とのコンタクトを得るには、ゲー
ト電極を形成した侵、素子領域および素予分離領域の全
体に絶縁層を形成し、その上から既に形成されている素
子領域に対するマスク合わせを行い、リソグラフィによ
りマスクを形成した後、絶縁層をエツチングによって、
素子領域にコンタクト孔を聞け、その後に配線材料を堆
積するのが一般的であった。Conventionally, in order to make contact between the device region and wiring, a gate electrode is formed, an insulating layer is formed over the entire device region and the preliminary isolation region, and a mask is aligned over the already formed device region. After forming a mask using lithography, the insulating layer is etched.
It was common to drill contact holes in the device area and then deposit wiring material.
しかしながら、上記半導体ｖｔ回においては、第４図に
示すように素子領域１３のパターンにコンタクト孔１４
のパターンを合わせてリソグラフィを行った後、コンタ
クト孔１４をエツチングによって開孔するために、素子
領域１３とコンタクト孔１４との位置合わせのズレを見
込んだ合わせ余裕１５が必要となり、この合わせ余裕１
５の存在が素子の高密度化の障害となっている。However, in the semiconductor Vt circuit, as shown in FIG.
In order to open the contact hole 14 by etching after performing lithography with the patterns of
The presence of 5 is an obstacle to increasing the density of devices.
通常、合わせ余裕１５は約０．５μｍ幅でとっているが
、その幅はりソグラフイにおける露光装置の精度に依存
し、しかもその精度の改善のスピードは素子の微細化の
スピードに比べるときわめて遅いため、素子が２μｍル
ールから１μｍルールに微細化されても、合わせ余裕１
５は依然として０．５μｍ程度の幅を必要とする。その
ために、素子の高密度化のＦ５害となり、高集積化に伴
って集積回路のチップ・ナイスが大きくなる主な原因の
一つとなっている。そしてチップ・サイズはパッケージ
の標準サイズＪ：り大ぎくできないという制限があるた
め、この問題は今後ま１゛ます重要なものとなる。Normally, the alignment margin 15 is set to a width of about 0.5 μm, but this width depends on the precision of the exposure equipment used in beam lithography, and the speed of improvement in precision is extremely slow compared to the speed of miniaturization of elements. , even if the device is miniaturized from the 2 μm rule to the 1 μm rule, the alignment margin is 1
5 still requires a width on the order of 0.5 μm. For this reason, it becomes an F5 impediment to the increase in the density of elements, and is one of the main reasons why the chip size of integrated circuits increases as the density increases. This problem will become even more important in the future because the chip size cannot be made larger than the standard package size J:.
本発明は、上記事情を考慮してなされたもので、素子の
高密度化の障害となっている、素子領域とコンタクト孔
との合わせ余裕をなくし集積回路の高集積化を実現する
ことができる半導体装置およびその製造方法を提供する
ことを目的とする。The present invention has been made in consideration of the above-mentioned circumstances, and can realize high integration of integrated circuits by eliminating the alignment margin between the element area and the contact hole, which is an obstacle to increasing the density of devices. The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the same.
上記目的を達成するため本発明による半導体装置は、半
導体基板に相対して形成されたソース領域およびドレイ
ン領域間の半導体基板表面に形成されたゲート酸化膜と
、このゲート酸化膜上に形成されたゲート電極と、この
ゲート電極の上面および側面に形成された絶縁層と、こ
の絶縁層により前記ゲート電極と絶縁され前記ソース領
域およびドレイン領域をそれぞれコンタクトする配線層
とを備えたことを特徴とする。In order to achieve the above object, a semiconductor device according to the present invention includes a gate oxide film formed on the surface of the semiconductor substrate between a source region and a drain region formed facing the semiconductor substrate, and a gate oxide film formed on the gate oxide film. It is characterized by comprising a gate electrode, an insulating layer formed on the upper surface and side surfaces of the gate electrode, and a wiring layer insulated from the gate electrode by the insulating layer and contacting the source region and the drain region, respectively. .
また、本発明による半導体装置の製造方法は、半導体基
板表面にゲート酸化膜を形成するｖＲｌの工程と、この
ゲート酸化股上にゲート電極となる）Ｑｆｆｉ体層を形
成する第２の工程と、このゲート電極となる導電体口上
に絶縁層を形成する第３の工程と、この絶縁層を上部に
のせたままゲート電極をパターニングする第４の工程と
、前記半導体基板に不純物を添加してソース領域および
ドレイン領域を形成する第５の工程と、前記半導体基板
に絶縁層を堆積し、この絶縁層を反応性イオンエツチン
グ法によりエツチングして、前記ゲート電極の側面に絶
縁層を形成する第６の工程と、前記ソース領域およびド
レイン領域をそれぞれコンタクトする配線層を形成する
第７の工程とを有することを特徴とする。Further, the method for manufacturing a semiconductor device according to the present invention includes a vRl step of forming a gate oxide film on the surface of a semiconductor substrate, a second step of forming a Qffi body layer (which will become a gate electrode) on this gate oxide layer, and a third step of forming an insulating layer on the conductor opening that will become the gate electrode; a fourth step of patterning the gate electrode with this insulating layer placed on top; and a step of adding impurities to the semiconductor substrate to form the source region. and a fifth step of forming a drain region, and a sixth step of depositing an insulating layer on the semiconductor substrate and etching this insulating layer by a reactive ion etching method to form an insulating layer on the side surface of the gate electrode. and a seventh step of forming a wiring layer that contacts the source region and the drain region, respectively.
本発明の一実施例による半導体装置の断面を第１図に示
す。半導体基板１上のフィールド酸化膜２により素子領
域が分離されている。この素子領域の半導体基板１表面
にはソース領域、ドレイン領域としてのｎ＋不純物領域
１１が形成されている。これらソース領域およびドレイ
ン領域間の半導体基板１上にはゲート酸化膜３が形成さ
れている。なおｎ＋不純物領域１１に隣接するチャネル
領域に接する部分にはより低濃度のｎ−不純物領域８が
形成され、いわゆるＬ Ｄ Ｄ （Ｌ １ｏｈｔｌｙＤ
ｏｏｅｄ Ｄ ｒａｉｎ）構造となっている。これ
により素子の劣化を防止している。ゲート酸化１ａ３上
にはゲート電極５ａが形成されているが、このゲート電
極５ａは上面および側面が酸化膜６および９ａにより覆
われている点に特徴がある。これによりｎ＋不耗物領域
１１とコンタクトする配線層１２をセルファラインで形
成することができる。FIG. 1 shows a cross section of a semiconductor device according to an embodiment of the present invention. Element regions are separated by a field oxide film 2 on a semiconductor substrate 1. On the surface of the semiconductor substrate 1 in this element region, an n+ impurity region 11 is formed as a source region and a drain region. A gate oxide film 3 is formed on the semiconductor substrate 1 between these source and drain regions. Note that an n- impurity region 8 with a lower concentration is formed in a portion in contact with the channel region adjacent to the n+ impurity region 11, and the so-called LDD (L1ohtlyD
It has an oed drain) structure. This prevents deterioration of the element. A gate electrode 5a is formed on the gate oxide 1a3, and the gate electrode 5a is characterized in that its upper surface and side surfaces are covered with oxide films 6 and 9a. Thereby, the wiring layer 12 in contact with the n+ consumable region 11 can be formed as a self-line.
このように本実施例によれば、ゲート電極５ａの上部と
側部とに酸化膜６，９ａとを形成し、ゲート電極５ａと
配線１２との絶縁を確保することにより、第２図に示す
ように、自己整合的に素子領域１３にコンタクト孔１４
を開孔することが可能となり、従来の合わせ余裕１５を
必要ないものとした。このことにより、１つのトランジ
スタを形成するに必要なｆＪ域は、従来のものより小さ
なものとなり、高集積化が可能となる。According to this embodiment, the oxide films 6 and 9a are formed on the upper and side parts of the gate electrode 5a to ensure insulation between the gate electrode 5a and the wiring 12, as shown in FIG. The contact hole 14 is formed in the element region 13 in a self-aligned manner as shown in FIG.
This makes it possible to drill holes, making the conventional alignment allowance 15 unnecessary. As a result, the fJ region required to form one transistor becomes smaller than that of the conventional transistor, and high integration becomes possible.
次にこの半導体装置の製造方法を第３図を用いて説明す
る。まず第３図（ａ）に示すように、比抵抗５Ω−υの
Ｐ型シリコンの半導体基板１の表面にフィールド酸化膜
２を形成した後、リソグラフィ工程によって、島状の素
子領域を形成する。Next, a method for manufacturing this semiconductor device will be explained with reference to FIG. First, as shown in FIG. 3(a), a field oxide film 2 is formed on the surface of a P-type silicon semiconductor substrate 1 having a specific resistance of 5 Ω-υ, and then an island-shaped element region is formed by a lithography process.
次に第３図（ｂ）に示すように、熱酸化処理を施し、半
導体基板１の素子領域の表面に膜厚１５０人のゲート酸
化膜３を形成した後、所定のしきい値電圧を得るためボ
ロン（８＋）イオン４を打ち込む。次に第３図（Ｃ）に
示すように、厚さ約２０００人のポリシリコン５を堆積
した後、リン拡散を温度９００℃で３０分間行って、ポ
リシリコン５を抵抗の低い導電体とし、その上にＣＶＤ
（Ｃｈｅｍｉｃａｌ Ｂａｐｏｒ Ｄｅｐｏｓｉｔｉ
ｏｎ ）法によってＩＩＩ厚約３０００Ａ＋７）第１（
Ｆ）ＣＶＤＭ化Ｉｌ！６ヲ堆積する。Next, as shown in FIG. 3(b), a thermal oxidation treatment is performed to form a gate oxide film 3 with a thickness of 150 nm on the surface of the element region of the semiconductor substrate 1, and then a predetermined threshold voltage is obtained. Boron (8+) ions 4 are implanted for this purpose. Next, as shown in FIG. 3(C), after depositing polysilicon 5 to a thickness of about 2000, phosphorus diffusion is performed at a temperature of 900° C. for 30 minutes to make polysilicon 5 a low-resistance conductor. CVD on top of that
(Chemical Bapor Deposit
on ) method III thickness approx. 3000A+7) 1st (
F) CVDM conversion Il! Deposit 6.
その後、第３図（ｄ）に示すように、リソグラフィ工程
により、第１のＣＶＤｆｉ化１１Ｊ化合１Ｊ６のせてい
るゲート電極５ａのパターニングを行い、次に加速電圧
５０ｋｅＶ、ドーズｆｆｉ２Ｘ１０１３ｃｍ’のリン（
Ｐ＋）イオン７の打込みを行って、表面の不純物濃度１
×１０１８１：１Ｉ−３の薄いｎ型領域、即ちｎ−不純
物領域８を形成する。次に第３図（ｅ）に示すように、
膜厚的５０００への第２のＣＶＤ酸化膜９を堆積した後
、反応性イオンエツチングによりこの第２のＣＶＤＩ化
膜９を約５０００Ａエツチングすると、第３図（ｆ）に
示すようにゲート電Ｆｉ５ａの（１部に側壁となる形状
で第２のＣｖＤ酸化膜９ａが残留する。その後、加速電
圧７０ｋｅＶ、ドーズｗ３ｘ １０１５ａｍ−２の砒素
（Ａｓ＋）イオン１０打込みによって、ソース・ドレイ
ン領域となるｎ 不純物領域１１を形成し、不純物イオ
ンを活性化するために、温度９００℃、３０分間のアニ
ールを行う。次に配線材料であるアルミニウム（Ａ１）
を堆積し、リソグラフィ工程によって配線ｖ３１２のパ
ターニングを行うと、素子領域のコンタクト孔のりソゲ
ラフイエ程を必要とすることなく、第１図（９）に示す
ように自己整合的にソース領域およびドレイン領域１１
との電気的導通が得られ、かつゲート電極５ａとの絶縁
が確保されている配ａ層１２が形成される。Thereafter, as shown in FIG. 3(d), the gate electrode 5a on which the first CVD fi 11J compound 1J6 is placed is patterned by a lithography process, and then the phosphorus (phosphorus
P+) ions 7 are implanted to reduce the surface impurity concentration to 1.
A thin n-type region of x10181:1I-3, that is, n- impurity region 8 is formed. Next, as shown in Figure 3(e),
After depositing the second CVD oxide film 9 to a thickness of 5,000 mm, this second CVDI film 9 is etched by about 5,000 A by reactive ion etching, resulting in a gate voltage Fi5a as shown in FIG. 3(f). A second CvD oxide film 9a remains in a shape that will become a side wall in a part of (a part). Then, by implanting 10 arsenic (As+) ions at an acceleration voltage of 70 keV and a dose of w3x 1015 am-2, an n impurity film that will become a source/drain region is formed. In order to form region 11 and activate impurity ions, annealing is performed at a temperature of 900° C. for 30 minutes. Next, aluminum (A1), which is a wiring material, is
When the wiring v312 is patterned using a lithography process, the source and drain regions 11 are formed in a self-aligned manner as shown in FIG.
A wiring layer 12 is formed which provides electrical continuity with the gate electrode 5a and ensures insulation from the gate electrode 5a.
なお上記実施例においては、いわゆるＬＤＤ構造の半導
体ＢＥが形成されるが第３図（ｄ＞の段階でイオン打込
み釘を増せば、ＬＤＤ構造でない通常の１４造の半導体
装置を形成することができる。In the above embodiment, a semiconductor BE having a so-called LDD structure is formed, but if the number of ion implantation nails is increased at the stage shown in FIG. .
、また、上記の実施例において、第３図（ｆ）の砒素（
Ａｓ＋）イオン１０打込みは、まずリン（Ｐ＋）イオン
の打込みを行い、しかる後に砒素（ＡＳ＋）イオンある
いはアンチモン（Ｓｂ＋）イオンを打込んでもよい。こ
れによって、いわゆるＱ［）［） （Ｇｒａｄｅｄ ［
）ｏｐｅｄ ［）ｒａｉｎ）構造が形成される。, In addition, in the above example, arsenic (
As+) ion 10 implantation may be performed by first implanting phosphorus (P+) ions, and then implanting arsenic (AS+) ions or antimony (Sb+) ions. This results in the so-called Q[)[) (Graded [
)oped [)rain) structure is formed.
以上の通り、本発明によれば、素子領域にコンタクト孔
を開孔するためのリングラフィ工程を必要とすることな
（、また素子領域とコンタクト孔とのマスク合わせズレ
を見込んだ合わせ余裕をもたせたパターン設計をするこ
となく、自己整合的に素子領域にコンタクト孔を形成す
ることができる。このことによって、例えばメモリーの
セルサイズを小さくすることができ、従って集積回路の
チップサイズの縮小化あるいは高集積化が達成される。As described above, according to the present invention, there is no need for a phosphorography process for forming contact holes in the element region (and there is no need for a phosphorography process to form contact holes in the element region). It is possible to form contact holes in the element region in a self-aligned manner without having to design a pattern.This allows, for example, to reduce the memory cell size, and therefore to reduce the chip size of integrated circuits or High integration is achieved.
とりわけ、１００万個を越えるトランジスタを集積する
超ＬＳＩ′においては、本発明による素子の高密度化が
有効である。In particular, the present invention is effective in increasing the density of elements in ultra-LSI's that integrate more than one million transistors.
さらに、本発明による半導体装置の製造方法は、素子の
偏傾性を高める上で必須とされているＬ Ｄ Ｄ （Ｌ
１ｏｈｔｌｙ Ｄ ｏｐｅｄ Ｄ ｒａｉｎ）構
造を作製するプロセスと適合性が良い。Furthermore, the method for manufacturing a semiconductor device according to the present invention has the advantage that L D D (L
It is well compatible with the process of fabricating a 100% open drain structure.
第１図および第２図はそれぞれ本発明の一実施例による
半導体装置の断面図および平面図、第３図は本発明の一
実施例による半導体装置の製造方法を示す工程図、第４
図は従来の半導体装置を示す平面図である。
１・・・半導体基板、２・・・フィールド酸化膜、３・
・・ゲート酸化膜、５・・・ポリシリコン、５ａ・・・
ゲートｆｆｉ極、６．９．９ａ・・・酸化膜、８・・・
ｎ−不純物領域、１１・・・ｎ十不純物領域、１２・・
・配線層、１３・・・素子領域、１４・・・コンタクト
孔、１５・・・合わせ余裕。
出願人代理人 猪 股 清
６１図
ａ
も ２ 困1 and 2 are a cross-sectional view and a plan view, respectively, of a semiconductor device according to an embodiment of the present invention, FIG. 3 is a process diagram showing a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG.
The figure is a plan view showing a conventional semiconductor device. 1... Semiconductor substrate, 2... Field oxide film, 3...
...Gate oxide film, 5...Polysilicon, 5a...
Gate ffi pole, 6.9.9a...Oxide film, 8...
n- impurity region, 11...n10 impurity region, 12...
- Wiring layer, 13... Element area, 14... Contact hole, 15... Alignment margin. Applicant's agent Kiyoshi Inomata Figure 61a also 2 problems
Claims (2)
ドレイン領域と、これらソース領域およびドレイン領域
間の半導体基板表面に形成されたゲート酸化膜と、この
ゲート酸化膜上に形成されたゲート電極と、このゲート
電極の上面および側面に形成された絶縁層と、この絶縁
層により前記ゲート電極と絶縁され前記ソース領域およ
びドレイン領域をそれぞれコンタクトする配線層とをそ
なえた半導体装置。1. A source region and a drain region formed opposite to a semiconductor substrate, a gate oxide film formed on the surface of the semiconductor substrate between these source and drain regions, a gate electrode formed on this gate oxide film, and a gate electrode formed on this gate oxide film. A semiconductor device comprising: an insulating layer formed on an upper surface and side surfaces of a gate electrode; and a wiring layer insulated from the gate electrode by the insulating layer and contacting the source region and the drain region, respectively.
程と、 このゲート酸化膜上にゲート電極となる導電体層を堆積
する第２の工程と、 このゲート電極となる導電体層の上に絶縁層を形成する
第３の工程と、 前記絶縁層を上部にのせたままゲート電極をパターニン
グする第４の工程と、 前記半導体基板に不純物を添加してソース領域およびド
レイン領域を形成する第５の工程と、前記半導体基板に
絶縁層を堆積し、この絶縁層を反応性イオンエッチング
法によりエッチングして、前記ゲート電極の側面に絶縁
層を形成する第６の工程と、 前記ソース領域およびドレイン領域とそれぞれコンタク
トする配線層を形成する第７の工程と、を有する半導体
装置の製造方法。2. A first step of forming a gate oxide film on the surface of the semiconductor substrate, a second step of depositing a conductive layer that will become the gate electrode on this gate oxide film, and an insulating layer formed on the conductive layer that will become the gate electrode. a third step of forming a layer, a fourth step of patterning a gate electrode with the insulating layer placed on top, and a fifth step of adding impurities to the semiconductor substrate to form a source region and a drain region. a sixth step of depositing an insulating layer on the semiconductor substrate and etching the insulating layer using a reactive ion etching method to form an insulating layer on the side surface of the gate electrode; and the source region and the drain region. and a seventh step of forming wiring layers in contact with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18100484A JPS6159750A (en) | 1984-08-30 | 1984-08-30 | Semiconductor device and manufacture of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18100484A JPS6159750A (en) | 1984-08-30 | 1984-08-30 | Semiconductor device and manufacture of the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6159750A true JPS6159750A (en) | 1986-03-27 |
Family
ID=16093050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18100484A Pending JPS6159750A (en) | 1984-08-30 | 1984-08-30 | Semiconductor device and manufacture of the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6159750A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6267873A (en) * | 1985-09-20 | 1987-03-27 | Sony Corp | Manufacture of semiconductor device |
| JPS63133574A (en) * | 1986-11-25 | 1988-06-06 | Seiko Epson Corp | Manufacture of mos-type semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147482A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Insulating gate type field effect transistor |
| JPS58115859A (en) * | 1981-12-28 | 1983-07-09 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-08-30 JP JP18100484A patent/JPS6159750A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56147482A (en) * | 1980-04-17 | 1981-11-16 | Nec Corp | Insulating gate type field effect transistor |
| JPS58115859A (en) * | 1981-12-28 | 1983-07-09 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6267873A (en) * | 1985-09-20 | 1987-03-27 | Sony Corp | Manufacture of semiconductor device |
| JPS63133574A (en) * | 1986-11-25 | 1988-06-06 | Seiko Epson Corp | Manufacture of mos-type semiconductor device |
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