JPS6246575A - Thin-film semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a lateral diffusion on the activation of an impurity implanted to a semiconductor substrate,and to form a thin-film transistor having short gate length by designing the thickness of a semiconductor film in an extent that the standard deviation of the range of implanting ions is added to the flight range of the ions. CONSTITUTION:A polycrystalline silicon film 11 is formed onto insulating substrate 10 through a thin-film manufacture technique such as CVD. The polycrystalline silicon film 11 is formed so that film thickness thereof is brought to an extent that the standard deviation DELTARP of the range RP of implanting ions is added to the range of the ions. The range RP changes by the kinds of impurities and implantation energy, and is determined so as to be positioned at approximately the center of the thickness of the polycrystalline silicon film. Accordingly, a space in which the impurity can be diffused in the depth direction is shortened, thus cutting down the heat treatment time for implanting ions, then inhibiting the lateral diffusion of the impurity.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a thin film semiconductor device, and particularly to a semiconductor device suitable for forming source and drain regions for a transistor.

<Conventional technology> In recent years, polycrystalline silicon thin film transistors (PolySi
Active efforts are being made to develop the application of TFTs to LSI memories. Such development is based on DRAM or S
The purpose is to utilize the various advantages of the SOI structure by using polycrystalline silicon thin film transistors in RAM memory cells.

<Problems to be Solved by the Invention> For example, in order to increase the storage capacity, it is necessary to reduce the number of memory cells, and for this purpose, the size of the polycrystalline silicon transistor must be reduced. An impediment to this shrinkage is the significant lateral diffusion of impurities implanted into the source and drain regions of transistors.

In other words, in a polycrystalline silicon substrate, grain boundaries are distributed within the thin film, unlike in the case of a single crystal, and as a result, the implanted impurity has the characteristic of quickly diffusing through the grain boundaries, resulting in a decrease in the effective channel length. This has become significant, impeding reduction in the gate length of transistors.

In particular, impurities implanted by ion implantation must be subjected to some heat treatment in order to become electrically activated in order to achieve their purpose within the silicon substrate. Such a heat treatment process achieves its purpose if impurities can be activated, but in actual processes using polycrystalline silicon substrates, there is a significant difference in the diffusion coefficient of impurities within grains and at grain boundaries. As diffusion progresses, the impurities result in a reduction in gate length.

Semiconductor film thickness is sufficiently thick (film thickness> implanted ion range Rp
), even if annealing is performed for a short time, the impurity 2 implanted near the surface of the polycrystalline semiconductor substrate 1 as shown in FIG. 2(a) will form crystal grains as shown in FIG. 2(b). It diffuses rapidly through the field, and also diffuses in the channel direction as well as in the depth direction.

Impurities distributed at grain boundaries as described above are generally considered to be electrically inactive, and even with this degree of annealing, activation does not progress. If you continue annealing further,
The impurity diffusion continues along the grain boundaries, and when viewed in the depth direction, it once reaches the bottom surface of the semiconductor thin film l, as shown in Figure 2 (C).
Thereafter, the impurities 2 distributed at the grain boundaries are diffused into the crystal grains 3 and activated.

However, at the time when activated impurities are generated by diffusion into the grains following diffusion in the depth direction, they have already diffused sufficiently in the lateral direction through the grain boundaries, so the second
As shown in Figure (d), the channel length must be significantly shorter than the mask dimension.

<Means to Solve the Problems> By solving the above-mentioned conventional problems and suppressing the lateral diffusion of impurities implanted into a semiconductor substrate during activation, a thin film transistor with a short gate length is constructed. The thickness of the polycrystalline semiconductor thin film is determined by the impurity ion implantation range Rp and its standard deviation Δ.
The thickness of the semiconductor layer should be approximately the same as that of Rp, which prevents lateral movement during impurity activation due to short-time heat treatment. Since the distance Rp is designed to be approximately equal to the standard deviation value ΔRp, the space in which impurities can be diffused in the depth direction is not short, and the heat treatment time for the implanted ions can be shortened and the lateral diffusion of impurities can be suppressed.

<Example> Figure 1 is a diagram illustrating the process of manufacturing a thin film transistor according to the present invention. A polycrystalline silicon film 11 is formed on θ using a thin film manufacturing technique such as CVD. The polycrystalline silicon film 11 is formed to have a thickness equal to the range Rp of implanted ions plus its standard deviation ΔRp.

The range Rp varies depending on the type of impurity and the implantation energy, and in this embodiment, the range Rp is determined to be located approximately at the center of the thickness of the polycrystalline silicon film.

Considering that the range into polycrystalline silicon is approximately the same as the range into crystalline silicon, when the oxide film thickness on the polycrystalline silicon film is about 300X, and when arsenic and boron are used as impurities, The range Rp and standard deviation ΔRp are as follows.

Below margin The film thickness is determined with reference to the above values.

A polycrystalline silicon film 11 formed on an insulating substrate 10,
After the gate oxide film 13 is formed on the surface, the channel region is covered with a mask 14 and p-layer or n-type impurity 2 is implanted by ion implantation to create impurity regions for the source and drain regions. .

At this time, since the thickness of the polycrystalline silicon film 11 is designed in advance to be about KRp + ΔRp as described above, the impurities dispersed in the grain boundaries are removed by annealing treatment for activation. As shown in Figure 1 (b), the diffusion in the depth direction is suppressed and it is quickly diffused into the grains, becoming an electrically active impurity (in the figure, white circles indicate inactive impurities and black circles indicate active impurities). .

Since the implanted ions are immediately activated, the effect of shortening the channel width is significantly reduced.

A thin film transistor is manufactured using the activated impurity region as a source or drain region.

Effects> According to the present invention, in a semiconductor device using a polycrystalline semiconductor thin film, the thin film can be made thinner by designing the semiconductor film thickness to be equal to the range of implanted ions plus its standard deviation. In addition, the effective channel length of the transistor is hardly reduced during heat treatment for electrically activating impurities, making it possible to reduce the transistor shape and to obtain a semiconductor device with easy manufacturing process control. can.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are cross-sectional views for explaining the process of an embodiment according to the present invention, and FIGS. 2(a) to (d) are cross-sectional views for explaining the conventional manufacturing process. be. lO: Insulating substrate 11: Polycrystalline silicon film 12: Impurity 13: Gate oxide film 14: Mask agent Patent attorney Yoshihiko Fukushi (and 2 others)

Claims (1)

[Claims] (1) In a semiconductor device in which a transistor is formed by activating impurity ions implanted into a polycrystalline semiconductor substrate, the film thickness of the polycrystalline semiconductor is expressed as polycrystalline semiconductor, where the range of the implanted ions is Rp and its standard deviation is ΔRp. A thin film semiconductor device characterized in that the thickness of the crystalline semiconductor is approximately equal to Rp+ΔRp.