GB1432309A - Semiconductor structures - Google Patents
Semiconductor structuresInfo
- Publication number
- GB1432309A GB1432309A GB844574A GB844574A GB1432309A GB 1432309 A GB1432309 A GB 1432309A GB 844574 A GB844574 A GB 844574A GB 844574 A GB844574 A GB 844574A GB 1432309 A GB1432309 A GB 1432309A
- Authority
- GB
- United Kingdom
- Prior art keywords
- substrate
- resistivity
- implanted
- igfet
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 abstract 5
- 150000002500 ions Chemical class 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- 239000011521 glass Substances 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000010849 ion bombardment Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
1432309 Semiconductor devices SIGNETICS CORP 25 Feb 1974 [2 March 1973] 8445/74 Heading H1K An enhancement-mode IGFET having a gate electrode of a semiconductor material such as polycrystalline silicon has a relatively low resistivity channel region formed, e.g. by ion inplantation, at the surface of a higher resistivity substrate. A process is described which uses conventional planar techniques in the manufacture of such an IGFET in a P-type substrate having a resistivity of 25 # cm. Prior to diffusion of the source and drain regions, e.g. from P-doped glass, the substrate area which the device is to occupy is subjected to B-ion bombardment through an oxide coating under conditions such that the peak density of implanted ions occurs at the substrate surface. The temperature of 700-1000‹ C. employed during the subsequent deposition of the polycrystalline Si gate electrodeissufficiently high to anneal bombardment-produced radiation damage but too low to cause significant migration of implanted ions into the bulk of the substrate. The device may be surrounded by a diffused or implanted P<SP>+</SP> isolation region. The invention is applicable to integrated circuits including both enhancement mode and depletion mode IGFETs, the latter differing from the former only in that the surface implantation of B-ions is omitted. Reference has been directed by the Comptroller to Specification 1,261,723.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US33758873A | 1973-03-02 | 1973-03-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1432309A true GB1432309A (en) | 1976-04-14 |
Family
ID=23321143
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB844574A Expired GB1432309A (en) | 1973-03-02 | 1974-02-25 | Semiconductor structures |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS5048880A (en) |
CA (1) | CA1010154A (en) |
DE (1) | DE2409899A1 (en) |
FR (1) | FR2220098A1 (en) |
GB (1) | GB1432309A (en) |
IT (1) | IT1007410B (en) |
NL (1) | NL7402828A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2518315A1 (en) * | 1981-12-10 | 1983-06-17 | Philips Nv | METHOD FOR FORMATION OF AREAS IMPLANTED BY SELF-ALIGNED IONS WITH SUPERPOSED INSULATING LAYER PARTS |
GB2123605A (en) * | 1982-06-22 | 1984-02-01 | Standard Microsyst Smc | MOS integrated circuit structure and method for its fabrication |
GB2199694A (en) * | 1986-12-23 | 1988-07-13 | Philips Electronic Associated | A method of manufacturing a semiconductor device |
-
1974
- 1974-02-25 GB GB844574A patent/GB1432309A/en not_active Expired
- 1974-03-01 DE DE19742409899 patent/DE2409899A1/en active Pending
- 1974-03-01 FR FR7407133A patent/FR2220098A1/fr not_active Withdrawn
- 1974-03-01 NL NL7402828A patent/NL7402828A/xx unknown
- 1974-03-01 CA CA193,839A patent/CA1010154A/en not_active Expired
- 1974-03-02 JP JP2471074A patent/JPS5048880A/ja active Pending
- 1974-04-08 IT IT2055774A patent/IT1007410B/en active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2518315A1 (en) * | 1981-12-10 | 1983-06-17 | Philips Nv | METHOD FOR FORMATION OF AREAS IMPLANTED BY SELF-ALIGNED IONS WITH SUPERPOSED INSULATING LAYER PARTS |
GB2123605A (en) * | 1982-06-22 | 1984-02-01 | Standard Microsyst Smc | MOS integrated circuit structure and method for its fabrication |
GB2199694A (en) * | 1986-12-23 | 1988-07-13 | Philips Electronic Associated | A method of manufacturing a semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
IT1007410B (en) | 1976-10-30 |
CA1010154A (en) | 1977-05-10 |
FR2220098A1 (en) | 1974-09-27 |
DE2409899A1 (en) | 1974-09-12 |
JPS5048880A (en) | 1975-05-01 |
NL7402828A (en) | 1974-09-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |