JPH02122570A - Nonvolatile memory and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve the quality of a film in an oxide film by forming a floating gate with a polycrystalline silicon containing boron and arsenic. CONSTITUTION:An SiO2 film 2 is formed on an active region of a p-type silicon substrate 1 and a polycrystalline silicon layer 3 is formed on the SiO2 film with a CVD process. Then an AsSG layer 4 is formed on the above layer 3 and arsenic is diffused into the silicon layer 3 by treating the above layer 4 with heat. After performing etchback of the AsSG film 4, an SiO2 film 5 is formed by oxidizing thermally the surface of the polycrystal silicon layer 3. Further, a polycrystal silicon layer 6 is formed on the SiO2 film 5 and after injecting impurities, the pattern of resist 7 is formed and then its anisotropic etching allows the silicon substrate 1 to be exposed. Then ion implantation of arsenic is performed in the regions 9 and 10 of the silicon substrate 1 and further, thermal oxidation is performed. Then an SiO2 film 8 is formed: on the exposed face of the silicon substrate 1; at sidewall faces of the polycrystal silicon layer 3; at the sidewall faces ad well as on the upper faces and the like of the polycrystal silicon layer 6. Then a PSG layer 11 is formed on the SiO2 film 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile memory such as an EPROM or an EEPROM, and a method for manufacturing the same.

[Summary of the Invention] The present invention provides a nonvolatile memory having a stacked structure of a floating gate formed on a semiconductor substrate and a control gate formed above the floating gate, wherein the floating gate contains boron and/or arsenic. By forming the floating gate with polycrystalline silicon, when the floating gate is heat-treated (thermal oxidation), the effect of accelerating grain growth in the polycrystalline silicon that forms the floating gate is suppressed, and the quality of the floating gate is improved. .

[Prior Art] Conventionally, EPROM and EEPROM are known as this type of nonvolatile memory. In these conventional nonvolatile memories, the floating gate is formed of polycrystalline silicon, and phosphorus (P) is used as an impurity. In this way, external contamination (for example, Na', etc.) is prevented by the getter effect of phosphorus.

[Problem to be solved by the invention] However, when phosphorus is diffused into the polycrystalline silicon that constitutes the floating gate and then subjected to heat treatment, the phosphorus ions become seeds and the grain size of the polycrystalline silicon increases. do.

As a result, unevenness occurs on the surface of the floating gate, and an oxide film formed by thermally oxidizing the floating gate also becomes uneven, resulting in a problem of deterioration of film quality.

The present invention was devised by focusing on these conventional problems, and aims to improve the quality of the oxide film between the floating gate and the control gate, thereby improving the reliability of the device. This is what we do.

[Means for Solving the Problems] Accordingly, the present invention provides a nonvolatile memory having a stacked structure of a floating gate formed on a semiconductor substrate and a control gate formed above the floating gate, in which the floating gate is The solution is to use polycrystalline silicon containing boron and/or arsenic.

"Operation" Boron and/or arsenic contained in the polycrystalline silicon that forms the floating gate is less likely to become a seed for grain growth during heat treatment, so it suppresses increase in grain size. Therefore, it is possible to prevent unevenness from occurring on the surface of the floating gate, and when an oxide film is formed by thermally oxidizing the floating gate, the quality of the film is improved.

[Example] Hereinafter, details of a nonvolatile memory and a manufacturing method thereof according to the present invention will be described based on an example shown in the drawings.

First, as shown in FIG. 1, an S film, which will become a first gate oxide film, is placed on an active region of a p-type silicon substrate 1, which is a semiconductor substrate.
An iOx film 2 is formed, and this Sin.

Polycrystalline silicon layer 3 which becomes a floating gate on top
is formed by CVD method.

Next, as shown in FIG. 2, arsenic silicate glass (which serves as a diffusion source for arsenic (As)) is placed on top of the polycrystalline silicon layer 3.
AsSG) B4 is formed by the CVD method, and then heat treatment is performed to diffuse arsenic into the polycrystalline silicon layer 3.

Next, as shown in FIG.
After etching back and removing and processing into a predetermined shape, the exposed surface of the polycrystalline silicon layer 3 is thermally oxidized to form a 5-hot film 5 that will become a second gate oxide film.

Furthermore, as shown in FIG. 4, a polycrystalline silicon layer 6 that will become a control gate is formed on the SiOx film 5 by CVD.
After implanting impurities, a resist 7 pattern is formed using a photolithography method, and anisotropic etching is performed using the resist 7 as a mask to expose the silicon substrate 1.

Next, the regions 9. which will become the sources and drains of the silicon substrate 1 exposed in this way. Arsenic is ion-implanted into the IO and thermal oxidation is performed to remove the exposed surface of the silicon substrate 1, the side wall surface of the polycrystalline silicon layer 3 forming the floating gate, and the side wall surface of the polycrystalline silicon layer 6 forming the control gate. A 5iOy film 8 is formed on the upper surface and the like. On this occasion,
Arsenic implanted into the source/drain regions 9.10 is activated by the heat of thermal oxidation.

Next, as shown in FIG.
form.

A nonvolatile memory manufactured by such a manufacturing method has a polycrystalline silicon layer 3 forming a floating gate.
Since arsenic is introduced into the material, grain growth due to thermal oxidation can be suppressed.

Therefore, unevenness is prevented from occurring in the 5iOz film 3 serving as the second gate oxide film and the 5iOt film 8 on the side surface.

In the above example, arsenic was introduced into the floating gate, but boron (B) may be introduced alone, or boron and arsenic may be introduced together to similarly suppress the acceleration of grain size expansion. It is possible to do so. Therefore, it is also possible to use boron silicate glass BSG or arsenic boron silicate glass (AsBSG) as a diffusion source.

Further, as in the above embodiment, P is applied on the 5iO1 film 8 covering the floating gate and the control gate.
By providing the SG layer I2, it is possible to deal with external contamination due to the getter effect of phosphorus (P).

In the above example, the SiOy film covering the floating gate was formed by thermal oxidation, but CVD
Of course, it may be deposited by a method.

Although the embodiments have been described above, the present invention is not limited thereto, and various design changes are possible.

[Effects of the Invention] As is clear from the above description, according to the present invention, since boron and/or arsenic are used as impurities in the floating gate, the increase in grain size is accelerated during heat treatment such as thermal oxidation. It is possible to suppress the occurrence of unevenness in the oxide film surrounding the floating gate. Therefore, there is an effect of improving the film quality of the oxide film.

Further, if an interlayer insulating film is formed using PSG after forming the control gate, an effect of preventing contamination from the outside can be obtained.

[Brief explanation of the drawing]

1 to 7 are cross-sectional views showing an embodiment of the method for manufacturing a nonvolatile memory according to the present invention. ■...Silicon substrate, 2...SiO! Membrane, 3...
Polycrystalline silicon layer, 4...As5G layer, 5...5i
Ot film, 6...polycrystalline silicon layer, 8...5iot
Film, 11...PSG layer. Figure 1: *A Diagram 7 of the cross-sectional circle of Mi, Ji [: Seike]

Claims (3)

[Claims] (1) In a nonvolatile memory having a stacked structure of a floating gate formed on a semiconductor substrate and a control gate formed above the floating gate, the floating gate is formed of polycrystalline silicon containing boron and/or arsenic. Non-volatile memory characterized by (2) In a method for manufacturing a nonvolatile memory having a stacked structure of a floating gate formed on a semiconductor substrate and a control gate formed above the floating gate, boron and/or Alternatively, a method for manufacturing a nonvolatile memory, comprising forming a diffusion source containing arsenic, and introducing boron and/or arsenic into the polycrystalline silicon by the diffusion source. (3) In a nonvolatile memory having a stacked structure of a floating gate formed on a semiconductor substrate and a control gate formed above the floating gate, the floating gate is formed of polycrystalline silicon containing boron and/or arsenic. A nonvolatile memory characterized in that an interlayer insulating film covering the control gate is formed of silicate glass containing phosphorus.