JPH02111062A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To form a region whose impurity distribution is uniform and where damage to a substrate is not caused by a method wherein a p<+>n<+> double diffusion layer is formed by a selective epitaxial method. CONSTITUTION:A substrate 101 is etched; a first trench 105 is formed. Then, a first half of a selective epitaxial growth operation to make a conductivity type identical to that of the substrate 101 is executed while an impurity of B is being doped; a p<+> region 106 is formed; a second half of the selective epitaxial growth operation to make the conductivity type opposite to that of the substrate 101 is executed while an impurity of P or As is being doped; an n<+> region 107 is formed; a second trench 108 whose size is smaller than that of the first trench 105 is formed. Then, an insulating film 109 for capacitor use is formed; after that, polycrystalline Si 110 is deposited; a cell plate is formed. A gap part remaining in the trench part 108 is filled and flattened by polycrystalline Si 111. Thereby, an impurity distribution is made uniform; it is possible to form a good impurity region where damage to the substrate 101 is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory having a trench-structured memory cell.

Conventional technology FIG. 3 shows a memory cell with a trench structure.
) is a plan view, and (b) is a cross-sectional view.
``The Complete Story of MDRAM'', Nikkei Microdevices, Bessatsuya 1. 1987).

This memory cell is a trench capacitor cell having a double diffusion layer of an n region 303 and a p region 304 formed in a p well 302 on a p substrate 301. here,
The word line 306 is made of polycrystalline silicon 305A and a backing A7 wiring 306B, and the pit line 306 is made of polycide.

A method for manufacturing this memory cell is shown in FIG. 4 (see the above-mentioned document).

(1) As shown in FIG. 4(-), a P well 302 and an element isolation region 303 are formed on a P substrate 301.

(2) As shown in Fig. 4(b), K, CV D Si
02 film 401 as a mask, RI E (Reac
A trench 402 is formed by etching Si using a tiveIon ttching method.

(3) As shown in M4 diagram (C), B S G (Bor
After depositing the BSG film 403, heat treatment is performed to diffuse B from the BSG film 403 to form a p+ layer 304 around the trench 402. In place of the SG film, a B ion implantation method is sometimes used.

(4) As shown in FIG. 4(d), As ions are implanted into the inside of the trench 402 (!I]lI wall, bottom), and then a shallow n-soil layer 303 is formed by heat treatment. Note that instead of ion implantation, A s -3OG (5
pin On Glass) film + “5G (Arse
(nicSilicate Glags) A solid phase diffusion method is sometimes used.

(6) As shown in FIG. 4(e), after forming an insulating film 404 for a capacitor, polycrystalline 5iaos is deposited to form a cell plate. The void portion still formed in the trench is flattened by the buried polycrystal 5i 406.

Problems to be Solved by the Invention However, in the above manufacturing method, the inside of the trench (side walls, bottom) is doped with impurities by ion implantation method or solid phase diffusion method using SOG film or SG film to form the memory cell part. However, it has the following problems.

■ In the ion implantation method, the trench opening area is constant, and as the trench gets deeper, the ion implantation angle becomes closer to perpendicular to the wafer, increasing the probability of forward scattering of ions, so the impurity dose is lower at the trench bottom than at the trench sidewalls. There were problems in that the amount increased and impurity distribution became non-uniform. Furthermore, damage to the substrate due to ion implantation cannot be ignored.

■ The solid phase diffusion method using SOG films, SG films, etc. has the disadvantage that it is difficult to control the amount of doped impurities, and it is difficult to uniformly form the SOG film and SG film in order to make the impurity distribution uniform. It had

The present invention takes into consideration the problems of the prior art, and provides a method for manufacturing a semiconductor memory that allows easy control of the amount of non-sewn materials doped inside the trench, causes no damage to the substrate, and provides a uniform impurity distribution. The purpose is to do.

Means for Solving the Problems The present invention includes a first step of etching a semiconductor substrate to form a first trench, and epitaxial growth inside the first trench (side wall, bottom) to form a first trench. a second step of forming a second trench smaller than the trench;
a third step of forming a gate oxide film on the surface of the second trench;
This is a method of manufacturing a semiconductor memory including the steps of 1 and 4, and a fourth step of forming commercially available polysilicon in the second trench covered with the oxide film.

Sakukawa The present invention uses the above-described manufacturing method to form an np impurity layer by epitaxial growth, resulting in uniform impurity distribution, greater control over impurity concentration, and no damage to the substrate, improving the performance of trench memory cells. bring about.

Example The present invention will be explained in detail below.

1) to (d) are process diagrams of a method for manufacturing a semiconductor memory in a first embodiment of the present invention.

(1) As shown in FIG. 1(a), a P substrate 101icP
A well 302 and an element isolation region 103 are formed.

(2) As shown in FIG. 1(b), using the insulating film 104 as a mask, RIE (Reactive Ion E)
First trenches 105 are formed by etching St.

(3) As shown in FIG. 1(c), in order to make the first half of the selective epitaxial growth the same conductivity type as the substrate, a p+ region 106 is formed by doping the entire B impurity (concentration N = 1017 to 1020d3), In the second half of the selective epitaxial growth, impurity doping is performed with P or As (N1017-1020 cm-3) to make the conductivity type opposite to that of the substrate.
n+ region 107 is formed, leaving a second trench 108 smaller in size than the first trench 105.

(4) As shown in FIG. 1(d), after forming the insulating film 109 for the capacitor, polycrystalline 5i 110 is deposited to form a cell plate. Furthermore, the void remaining in the trench portion is flattened with buried polycrystalline Si 111.

As described above, according to this embodiment, since the p+n+ diffusion double layer is formed by epitaxial growth, the impurity distribution becomes uniform and a good impurity region is formed without causing damage to the substrate.

In addition, when performing epitaxial growth, an electrically inactive ■
Low pressure epitaxial growth (100 Torr) is used to correct strain with group elements and to prevent unnecessary autodoping.
(below) is required, and light irradiation (
However, it is effective to make the irradiation wavelength smaller than the minimum diameter of the trench 108) or to pre-bake.

Figures 1(C') to (e') utilize the fact that the p+ region 106 in Figure 1(c) has a uniform impurity distribution due to high concentration solid phase diffusion for the purpose of element isolation and large capacity. Figure 1 (a) ~
This is a modification of (d).

(1)-(2) A trench 106 is formed in Si using the same process as in FIGS. 1(a) and 1(b).

(3') As shown in FIG. 1 (C'), the BSG film 123
After depositing BSG film 123, heat treatment is performed, and BSG film 123 is
is diffused to form p+ region 124 around trench 105.

(4') As shown in Figure 1 (d'), doping with P or As impurity (N=1017~1020cTrT3)
Selective epitaxial growth is performed while keeping the n+ region 12
form 7. At time 0, a second trench 128 of smaller dimensions than the first trench 106 remains.

(5') As shown in FIG. 1(e'), after forming an insulating film 129 for a capacitor, polycrystalline 5i 130 is deposited to form a cell plate. still.

The void remaining in the trench is filled with buried polycrystalline St.
Planarization is performed by step 131.

FIGS. 2(a) to 2(d) are process diagrams of a method for manufacturing a semiconductor memory showing a second example of the present invention.

The growth rate of the epitaxial film is surface index <110).

The speed is faster in the order of <100> and <111>. Therefore, the case where the surface index of the bottom of the trench is <111> and the surface index of the upper side wall of the trench is (110) is shown below.

(1) As shown in FIG. 2(,), a P well 202 and an element isolation region 203 are formed on a P substrate 201. .

(2) As shown in FIG. 2('b), Si is etched by RIE using the insulating film 204 as a mask to form a first trench 205 (the angle between the l11U wall and the bottom of the trench is 9o0). larger).

(3) As shown in Figure 2(c), the first half of the selective epitaxial growth is doped with B as an impurity (N=1o17~1
o20d3) forming a p+ region 206 while
The second half of the selective epitaxial growth is performed while impurity doping with P or As (N=1d7 to 1020i3) to form an n+ region 207, leaving a second trench 208 smaller in size than the first trench.

(4) As shown in FIG. 2(d), after forming an insulating film 209 for the capacitor, polycrystalline Si 210 is deposited to form a cell plate.

As described above, according to this practical example, a p + n - double diffusion layer is formed by epitaxial growth using a trench in which the angle between the side wall and the bottom is 9oO or more, taking into account the difference in the plane index of the crystal plane. It is possible to compensate for the difference in epitaxial growth rate caused by the difference in surface index, and to form a high-quality impurity region with a uniform impurity distribution and no damage to the substrate.

As described in detail, according to the present invention, the performance of the trench-structured memory cell is improved by forming the p+n- double diffusion layer by the selective epitaxial method, so that the impurity distribution is uniform, and the impurity distribution is uniform.
It can be used as an area where damage to the substrate is high, and its practical effect is great.

[Brief explanation of the drawing]

1j;i is a process diagram of a method for manufacturing a semiconductor memory according to one embodiment of the present invention; FIG. 2 is a process diagram of a method for manufacturing a semiconductor memory according to another embodiment of the present invention; FIG. is a diagram of a trench memory cell of a conventional semiconductor memory, and FIG. 4 is a diagram of a trench memory cell of a conventional semiconductor memory.
1 is a process diagram of a conventional method for manufacturing a semiconductor memory having a double diffusion layer inside a trench; FIG. 105.205...First trench, 108°1
28.208...Second trench, 106°12
4.206...p+ region 107,127°2
07・・・・・・n+Name of territorial agent Patent attorney Shigetaka Awano and 1 other person (d
) Figure 1 (a) (b) (d') Figure 1 (e) (d) Figure 2 (a) (b) Figure 3 (a) 4.6 Toughness Figure 4 (a) (b ) Figure 4 (C) (d)

Claims (2)

[Claims] (1) A first step of etching a semiconductor substrate to form a first trench, and a second step of forming a second trench smaller than the first trench by epitaxial growth inside the first trench. and a third step of forming a gate oxide film on the surface of the second trench, and a fourth step of forming polysilicon for an electrode on the second trench covered with the oxide film. A method for manufacturing a semiconductor memory characterized by: (2) A fifth step in which the second step is doping with an impurity of the same conductivity type as the semiconductor substrate in the first half of epitaxial growth.
2. The method of manufacturing a semiconductor memory according to claim 1, further comprising a sixth step of doping with an impurity of a conductivity type opposite to that of the substrate in the latter half of epitaxial growth.