JP3027743B2 - Manufacturing method of stacked capacitor for DRAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stacked capacitor which can be used for a DRAM (Dynamic RAM).

[0002]

BACKGROUND OF THE INVENTION Improving device performance and reducing manufacturing costs are major goals of the semiconductor industry. These goals have already been achieved in the sub-micron range and have been applied to the manufacture of semiconductor memory chips. The submicron technology causes a decrease in the performance of capacitance and resistance, but this technology can be used to form similarly small chips on small devices, and when it is formed on large devices. And the same level of integration can be achieved. That is, a large number of smaller and more highly integrated chips can be obtained using a substrate of a certain size, which results in a reduction in manufacturing cost per chip.

[0003] It is difficult to increase the capacitance by using a pattern having a small size or a submicron pattern in manufacturing a DRAM device having a stacked capacitor structure. One DRAM memory cell is
It usually contains a stacked capacitor structure, is located on the gate transistor, and is connected to the source of the gate transistor. However, as the size of the gate transistor is reduced, the size of the stacked capacitor structure is also restricted.

Therefore, in order to increase the capacitance of a stacked capacitor structure having two electrodes and separated by a dielectric layer, it is necessary to adopt one of the following methods. That is, whether to reduce the thickness of the dielectric layer or increase the surface area of the capacitor. The former method of reducing the thickness of the dielectric layer increases the risk in terms of reliability and yield when an ultra-thin dielectric layer is used. Also, the latter method of increasing the surface area of the stacked capacitor structure is limited by the surface area of the underlying gate transistor. The advantage of DRAM technology is that memory cells with a degree of integration of about 6.4 billion or more can be formed on each chip. However, as the degree of integration increases, the area for arranging gate transistors on each memory cell becomes smaller. As a result, it is necessary to reduce the area occupied by the stacked capacitors.

The main methods for simultaneously reducing the size of a stacked capacitor and maintaining or increasing the capacitance are as follows.
A rough silicon layer or a silicon layer in which hemispherical particles protrude (hereinafter abbreviated as HSG shape) is used. For example, Thakur et al., US Pat.
No. 6,531, there is disclosed a process of forming an HSG-like silicon layer on a lower electrode of a capacitor. This method includes a method of depositing an amorphous silicon layer used for forming an HSG-like silicon layer. It does not include a surface conditioning step, which is performed on the lower electrode in advance. Lack of the pre-cleaning step before depositing the amorphous silicon layer causes a decrease in the adhesion between the amorphous silicon layer and the lower electrode. Zahurk et al.
U.S. Pat. No. 5,639,685 discloses a pre-cleaning step which is performed prior to depositing a polysilicon layer used as an underlying electrode, wherein the HSG-like silicon It is not performed before depositing the amorphous silicon layer used to form the layer.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide an HS
The use of a lower electrode having a surface layer of G-like silicon is intended to increase the surface area of a stacked capacitor applied to a DRAM device. To make a substantial improvement in the adhesion between them.

[0007]

In view of the above problems, in the present invention, the surface area of the electrode structure is increased by forming an HSG-like silicon layer on the base of the polysilicon lower electrode, thereby increasing the surface area of the DRAM capacitor. The purpose is to increase the capacity. A feature of the present invention is that a pre-cleaning step is performed before depositing a heavily doped amorphous silicon layer on the already patterned polysilicon lower electrode base. The heavily doped amorphous silicon layer used here can prevent the migration of silicon. Unless a heavily doped amorphous silicon layer is formed, a native oxide film is formed at the interface between the HSG-like silicon layer and the underlying silicon layer, and the HSG-like silicon layer is peeled off. This will cause a phenomenon. Therefore, prior to the formation of the HSG-like silicon layer, performing a pre-cleaning step first and then depositing a heavily doped silicon layer can prevent the formation of a natural oxide film, and as a result, a peeling phenomenon occurs. Of the HSG-like silicon layer and the underlying silicon layer can be prevented from lowering.

Another feature of the present invention is the use of the same furnace on which the heavily doped amorphous silicon layer is deposited, and the use of a lightly doped or undoped amorphous silicon. The purpose of the present invention is to obtain a roughened HSG-like surface layer by depositing a high quality silicon layer and subsequently performing a seeding / annealing step.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The method of forming an HSG-like silicon layer on the surface of a lower electrode according to the present invention includes a pre-cleaning step under acidic conditions; and forming a thin amorphous silicon layer heavily doped with impurities. Performing a step of forming an undoped amorphous silicon layer or an amorphous silicon layer doped with a small amount of impurities; and an annealing / seeding step.

Hereinafter, the present invention will be described in more detail. First, on a semiconductor substrate, a thin gate insulating layer; a polysilicon gate structure covered with an insulating layer; a source / drain region lightly doped with impurities; and an insulating layer located on a side wall of the polysilicon gate structure. Forming a gate transistor comprising isolation walls; and source / drain regions heavily doped with impurities.

Next, an insulating layer is formed and planarized. Subsequently, a contact hole for a lower electrode is opened in the insulating layer to expose a source region of the gate transistor. The polysilicon lower electrode base is formed so that the contact hole is completely filled and a part of the polysilicon lower electrode base covers the surface of the insulating layer. After performing a pre-cleaning step with diluted hydrofluoric acid, a thin amorphous silicon layer doped with a large amount of impurities is formed, and then an amorphous silicon layer doped with no impurities or doped with a small amount of impurities is formed. A silicon layer is formed. Preferably, an amorphous silicon layer doped with a small amount of impurities is formed. continue,
Using the same furnace as that for depositing the amorphous silicon layer, an annealing / seeding step is performed as it is, and the amorphous silicon layer which is not doped with impurities at all or the impurity is doped at a small amount. The amorphous silicon layer is changed to a roughened HSG-like silicon layer. Next, a dielectric layer is formed on the HSG-like silicon layer, and then a polysilicon layer is formed thereon. This polysilicon layer is patterned to form an upper electrode for a stacked capacitor. And finally, the dielectric layer, HSG
The silicon layer and the thin amorphous silicon layer heavily doped with impurities are sequentially etched to form a lower electrode structure for a stacked capacitor. In the present invention, a short-circuit phenomenon is prevented from occurring between closely arranged capacitors by forming a lower electrode base having a narrow width so that an amorphous silicon layer can be additionally deposited. be able to.

In order to clarify other objects and advantages of the present invention, preferred embodiments will be described below with reference to specific examples.

For the purpose of increasing the surface area and capacitance of the stacked capacitor, the roughened HS
A method of manufacturing a stacked capacitor for a DRAM having a G-shaped silicon layer will be described in detail below. The gate transistor used for the DRAM in the present invention is an N-channel. However, the stacked capacitor having the increased surface area according to the present invention can be applied to a P-channel gate transistor.

As shown in FIG. 1, the direction of the single crystal is <1.
00> was used. next,
An oxidation-resistant insulating mask (not shown in the figure) having a specific pattern was formed on the semiconductor substrate 1, and after protecting other element regions, a field oxide film 2 was formed by thermal oxidation. . As the oxidation-resistant insulating mask, for example, a composite layer of silicon nitride and silicon oxide can be used. After forming the field oxide film 2 having a thickness of 2000 to 5000 mm, the composite insulating mask was removed. At the time of removal, a hot phosphoric acid solution was used for silicon nitride, and a buffer solution of hydrofluoric acid was used for silicon oxide.
After performing a series of wet cleaning, a gate insulating layer 3 made of silicon oxide and having a thickness of 40 ° to 200 ° was formed under a temperature of 750 ° C. to 1050 ° C. and oxygen vapor using a thermal oxidation method.

Subsequently, a temperature of 500
A polysilicon layer 4 having a thickness of 500 to 4000 ° C. was formed at a temperature of 700 ° C. to 700 ° C. This polysilicon layer is formed by depositing arsenic ions or phosphorus ions at an energy of 10 keV or more and 80 keV or less and a dose of 1 × 10 ¹³ after growth.
Ion implantation may be performed in a range of not less than 1 cm ^{−2 and not} more than 1 × 10 ¹⁶ cm ⁻² , or hydrogen arsenide or hydrogen phosphide may be mixed with silane and disilane and doped simultaneously with the growth of the polysilicon layer. Is also good. If necessary, polycide (metal silicide-polysilicon) may be used in place of the polysilicon layer 4 to lower the word line resistance. This can be achieved by forming a tungsten or titanium silicide layer over the polysilicon layer.

Next, a low pressure CVD method or a plasma CV
Using method D, a first insulating layer 5 made of silicon oxide and having a thickness of not less than 600 ° and not more than 2000 ° was grown to be a cap insulating layer. The first insulating layer 5 may be formed by growing a silicon nitride layer having a thickness of not less than 600 ° and not more than 2000 ° by using a low pressure CVD method or a plasma CVD method.

Next, CH 2 is applied to the first insulating layer 5 by the conventional light exposure and reactive ion etching methods.
As shown in FIG. 1, a polysilicon gate structure composed of the polysilicon layer 4 covered with the first insulating layer 5 is formed by using F ₃ as the etching agent for the polysilicon layer 4 and Cl ₂ as the etching agent. Formed. The photoresist pattern was then removed using plasma oxygen ashing and a wet cleaning method.

Next, the energy is 5 KeV or more and 60 KeV.
Below, dose amount 1 × 10¹³cm^-2 More than 1 × 10¹⁵cm
^-2By implanting phosphorus ions in the following range,
To form source / drain regions 6 which are only doped
Was. Next, a low pressure CVD method or a plasma CVD method is used.
At a temperature between 400 ° C and 850 ° C, silicon oxide
Second thickness of not less than 1500 mm and not more than 4000 mm
An edge layer was deposited. Subsequently, anisotropic reactive ion etching
The second insulating layer is etched using a etching method.
And insulation on the sidewalls of the polysilicon / polycide gate structure
An isolation wall 7 was formed. At this time CHF_Three The etching agent
Used as The insulating isolation wall 7 is made of silicon nitride
It can also be formed.

Subsequently, the energy is 30 KeV or more and 100
At KeV or less, dose amount 1 × 10 ¹⁴ cm ⁻² or more and 5 × 10 ¹⁶
Arsenic ions were implanted in the range of cm ⁻² or less to form heavily doped source / drain regions 8. The result of performing the above series of steps is as shown in FIG.

Using a low pressure CVD method or a plasma CVD method, at a temperature of 600 ° C. or more and 800 ° C. or less, silicon oxide, boron phosphate silicate glass (BPS)
G), and a third insulating layer 20 made of any one of phosphate silicate glass (PSG) and having a thickness of 3000 ° to 10,000 ° is deposited. This third insulating layer 20 is made of BP
For an SG layer, diborane and phosphine are added using tetraethylorthosilicate (hereinafter abbreviated as TEOS) as a growth source, and for a PSG layer, TEO as a growth source is used.
Growth was achieved by adding only phosphine to S.
Subsequently, the third insulating layer 2 is formed using a chemical mechanical polishing method.
0 was subjected to a planarization treatment to provide a smooth surface for further layer deposition and patterning.

Next, a contact hole 9 for a lower electrode is opened in the third insulating layer 20 by using CHF ₃ as an etching agent and the conventional techniques of light exposure and reactive ion etching to form a large number of holes. The exposed source / drain region 8 is exposed. The result of performing the above series of steps is as shown in FIG.

As shown in FIG. 2, using a low pressure CVD method, a temperature of 500.degree.
A polysilicon layer having a thickness of not less than 000 ° and not more than 10,000 ° was deposited to completely fill the contact hole 9 for the lower electrode. This polysilicon layer was formed while doping with a mixture of silane and hydrogen arsenide or hydrogen phosphide. Next, using a conventional technique of light exposure and reactive ion etching using Cl ₂ as an etching agent, a polysilicon lower electrode base 10a is placed at the position of the lower electrode contact hole 9 and a polysilicon lower electrode base 10a is formed next to the contact hole 9 for the lower electrode. Another polysilicon lower electrode base 10b was formed. This structure is shown in FIG.

Polysilicon lower electrode bases 10a, 10b
Must be set to be narrower than the width of the lower electrode structure finally required. This is because an amorphous silicon layer will be added to both sides of the polysilicon lower electrode bases 10a and 10b in a later step. At this stage, the width of the space 30a sandwiched between the two polysilicon lower electrode bases was not less than 1500 ° and not more than 4000 °. And using plasma oxygen ashing and wet cleaning methods,
The photomask used to isolate the two polysilicon lower electrode bases 10a, 10b was removed.

Next, a pre-cleaning step, which is a key point of the present invention, was performed. First, a pre-cleaning step is performed at room temperature (about 25 ° C.) using a diluted hydrofluoric acid solution (the molar ratio of hydrogen fluoride to deionized water is 1: 100 to 200),
The natural oxide film was removed from the surfaces of the polysilicon lower electrode bases 10a and 10b. Subsequently, a highly doped amorphous silicon layer 11 having a thickness of 50 ° to 1000 ° was deposited at a temperature of 500 ° C to 550 ° C in a furnace for low pressure CVD. This amorphous silicon layer 11
Was doped simultaneously with deposition by a low pressure CVD method using silane or disilane to which hydrogen phosphide was added.
As a result, as shown in FIG.
Amorphous silicon layer 11 having a surface concentration exceeding 10 ²⁰ cm ^-3
was gotten. Since the impurity concentration required for saturation is expressed as a function of the deposition temperature, an impurity concentration of 4 × 10 ²⁰ cm ^-3 or more should be obtained at a deposition temperature of 500 ° C. to 550 ° C. become.

In order to prevent the movement of silicon that occurs in the seeding / annealing step performed to form the HSG-like silicon layer, it is necessary to dope the amorphous silicon layer 11 with a large amount of impurities. If the amorphous silicon layer 11 is doped with only a small amount of impurities,
Silicon migration may occur. This amorphous silicon layer 11 is connected to the polysilicon lower electrode bases 10a and 10b.
As a result, the width of the space 30b sandwiched between the two polysilicon lower electrode bases was reduced (see FIG. 3).

Another amorphous silicon layer 12a serving as a seed layer of the HSG-like silicon layer is formed under the same reduced pressure C as used for depositing the amorphous silicon layer 11 heavily doped with impurities.
Using a furnace for VD, it was deposited as it was. The amorphous silicon layer 12a is formed at a temperature lower than 550 ° C.
It was deposited to a thickness of 0 ° or more and 500 ° or less. The amorphous silicon layer 12a may be undoped, doped with a small amount of impurities, or a composite of a doped layer and an undoped layer. Doping can be performed by mixing hydrogen phosphide with silane or disilane simultaneously with the deposition. As a result, the amorphous silicon layer 12a
The impurities were not contained or the impurity concentration was 4 × 10 ²⁰ cm ⁻³ or less. The result is as shown in FIG. As a result, the polysilicon lower electrode base 10
The width of the space 30c between a and 10b is greatly reduced,
It became not less than 00 ° and not more than 3000 °.

Next, the same low pressure CVD furnace is used as it is, and a key seeding / annealing step is performed to form an HSG-like silicon layer 12 as shown in FIG.
b was formed. First, on the amorphous silicon layer 12a,
Using silane or disilane under nitrogen atmosphere,
A seed crystal of G was formed. At this time, the seeding concentration with silane and disilane is 1.0 × 10 ⁻³ mol · m ⁻³ or less, the temperature is 550 ° C. or more and 580 ° C. or less, and the pressure is less than 1 Torr and 5 minutes to 120 minutes. Seeding was done within. Subsequently, annealing is performed in a nitrogen-only atmosphere at a temperature of 550 ° C. or more and 580 ° C. or less within 120 minutes to form an HSG-like layer 12b as shown in FIG.
Was formed. From the amorphous silicon layer 11 under the HSG-like silicon layer 12b, the HSG-like silicon layer 12
Diffusion (doping) of the impurity supplied to b can prevent migration of silicon from occurring in the annealing step. If silicon migration occurs, HS
An obstacle occurs in the formation of the G-shaped silicon layer 12b.

The space 30c sandwiched between the two polysilicon lower electrode bases is formed to a desired width by first forming the polysilicon electrode base to be narrow and then performing a subsequent amorphous silicon layer deposition process. I was able to narrow it. In addition, the adhesion of the HSG-like silicon layer 12b to the polysilicon lower electrode base was improved by sandwiching the heavily doped amorphous silicon layer 11 therebetween.

Next, a dielectric layer 13 was formed on the HSG-like silicon layer 12b. The dielectric layer 13 is made of ONO (silicon oxide-silicon oxide-silicon oxide) or NO (oxide
It is made of a material having a high dielectric constant, such as silicon nitride. ON
To form the O layer, first, a silicon dioxide layer having a thickness of 10 ° to 50 ° was grown on the HSG-like silicon layer 12b, and then a silicon nitride layer having a thickness of 10 ° to 60 ° was deposited. Subsequently, a thermal oxidation process was performed on the silicon nitride layer to form a silicon oxynitride layer on the silicon oxide. This silicon oxynitride layer was equivalent to a silicon oxide layer having a thickness of about 40 ° to 80 °. The results are as shown in FIG.

Finally, using a low pressure CVD method or the like,
At a temperature of not less than 700 ° C and not less than 500 ° C
A polysilicon layer of less than 00 ° was deposited. The polysilicon layer was doped simultaneously with the deposition by mixing hydrogen phosphide with silane or disilane. Next, the polysilicon layer is patterned using Cl ₂ as an etchant and using the conventional processes of light exposure and reactive ion etching to form a polysilicon upper electrode 14 as shown in FIG. Formed.

Using a similar photomask (not shown), CHF ₃ is used for the dielectric layer 13 and Cl ₂ is used for the HSG-like silicon layer 12b and the amorphous silicon layer 11, respectively. The etching was continued to complete the lower electrode structure 15. Stacked capacitor structure 1
6 has a polysilicon upper electrode 14;
A dielectric layer 13 and a lower electrode structure 15 are provided.
A space 30d having a width of {2000 to 2,000} was formed.
Finally, the photoresist was removed by plasma oxygen ashing and wet cleaning.

While the preferred embodiments have been disclosed above, they are not intended to limit the scope of the invention in any way, and anyone skilled in the art will be able to make the same without departing from the spirit and scope of the invention. It will be understood that various modifications can be made in the form and details.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a state in which a contact hole for a lower electrode is formed.

FIG. 2 is a cross-sectional view showing a state where a lower electrode is patterned.

FIG. 3 is a diagram showing a state in which a heavily doped amorphous silicon layer is deposited.

FIG. 4 is a cross-sectional view showing a state where an amorphous silicon layer for forming an HSG-like silicon layer is formed.

FIG. 5 is a cross-sectional view showing a state where an HSG-like silicon layer is formed.

FIG. 6 is a sectional view showing a state where a dielectric layer is formed.

FIG. 7 is a cross-sectional view showing a state where an upper electrode is formed.

[Explanation of symbols]

Reference Signs List 1 p-type semiconductor substrate 2 field oxide film 3 gate insulating layer 4 polysilicon layer 5 first insulating layer 6 (N) source / drain region doped with a small amount of impurity 7 insulating isolation wall 8 (N ⁺ ) large amount of impurity Source / drain regions 9 doped with lower electrode 9 contact holes for lower electrode 10a, 10b base of lower electrode of polysilicon 11 amorphous silicon layer heavily doped with impurities 12a amorphous silicon layer 12b HSG-like silicon layer 13 dielectric Layer 14 Polysilicon upper electrode 15 Lower electrode 16 Stacked capacitor 20 Third insulating layer 30a, 30b, 30c, 30d Space between polysilicon electrode bases (or structures)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-5805 (JP, A) JP-A-10-56155 (JP, A) JP-A-6-204426 (JP, A) JP-A 8- 306646 (JP, A) JP-A-10-112530 (JP, A) JP-A-5-67730 (JP, A) JP-A-5-90529 (JP, A) JP-A-6-5805 (JP, A) JP-A-8-298312 (JP, A) JP-A-9-298278 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (29)

(57) [Claims] 1. A stacked capacitor for a DRAM device.
A step of forming a lower electrode base on the semiconductor substrate, and performing a wet pre-cleaning under acidic conditions to form the lower electrode.
Removing a native oxide film on the surface of the pole base; and forming a first amorphous layer doped with impurities on the lower electrode base.
Depositing a silicon layer and checking whether the first amorphous silicon layer is doped.
Or impurities at a concentration lower than that of the first amorphous silicon layer.
For depositing a second amorphous silicon layer doped with Pd
And a second amorphous silicon layer having a hemispherical particle protruding.
Converting to a concrete layer.
Sensor manufacturing method. 2. A method of manufacturing a stacked capacitor for a DRAM device on a semiconductor substrate, comprising: a polysilicon gate structure formed on a gate insulating layer; and source / drain regions formed in the semiconductor substrate. Providing a gate transistor on the semiconductor substrate, the method including: providing a contact hole for a lower electrode in an insulating layer to expose a surface of a source region; and allowing the contact hole for the lower electrode to be completely filled. Forming a lower electrode base on the surface of the insulating layer and forming a first space between the lower electrode bases; performing a wet pre-cleaning under acidic conditions to form a first space on the surface of the lower electrode base; a step of removing a natural oxide film; not on the lower electrode base and between said first space
Depositing a first doped amorphous silicon layer;
Forming a second space between the lower electrode bases; and do not dope the first amorphous silicon layer.
Rui not at lower concentrations than the first amorphous silicon layer
Depositing a second layer of pure amorphous silicon,
Forming a third space between the lower electrode bases; and performing seeding / annealing so that hemispherical particles protrude (HSG-like) from the second amorphous silicon layer.
Converting to a silicon layer; forming a dielectric layer on the HSG-like silicon layer; depositing a polysilicon layer on the dielectric layer; forming a photoresist pattern; Using the resist pattern as a photomask,
Patterning the polysilicon layer to form a polysilicon upper electrode of the stacked capacitor; similarly using the photoresist pattern as a photomask, forming the dielectric layer, the HSG-shaped silicon layer, the first
Patterning the amorphous silicon layer in order to form a lower electrode structure of the stacked capacitor, and forming a fourth space between the lower electrode structures. 3. The step of depositing the first amorphous silicon layer,
Depositing the second amorphous silicon layer;
Of amorphous silicon layer to HSG-like silicon layer
3. The process according to claim 1, wherein the steps are performed in the same furnace.
Manufacturing method for tacky capacitors . 4. A method according to claim 1, wherein said lower electrode base is made of polysilicon, and said polysilicon layer has a temperature of 500.degree.
Below, using a low pressure CVD method, a thickness of 1000
A stack according to any of the preceding claims , wherein the stack is a polysilicon layer that is doped simultaneously with the deposition by depositing below 0000 ° and depositing a mixture of hydrogen phosphide or hydrogen arsenide in silane or disilane. Manufacturing method of capacitor. Wherein said lower electrode base portion, an anisotropic refractory ion etching using a Cl ₂ as the etching agent is formed by performing the polysilicon layer claims 1-3 Neu
A method for manufacturing a stacked capacitor according to any of the above. 6. The method according to claim 2 , wherein the width of the first space between the lower electrode bases is not less than 1500 ° and not more than 4000 °. 7. The wet pre-cleaning step under acidic condition, which is performed on the base of the lower electrode, comprises the step of removing a diluted hydrofluoric acid solution having a volume ratio of hydrogen fluoride to deionized water of 1: 100 to 200. The method for producing a stacked capacitor according to any one of claims 1 to 3, wherein the method is used. 8. The method according to claim 1, wherein said first amorphous silicon layer is formed under reduced pressure C.
Using a furnace for VD at a temperature of 500 ° C or more and 550 ° C or less,
Deposited at a thickness of 50 ° or more and 1000 ° or less, and a mixture of silane or disilane mixed with hydrogen phosphide, thereby being doped simultaneously with the deposition, and having a surface impurity concentration of 4 × 10 ²⁰ cm ⁻³ or more. At saturation level
A method for manufacturing the stacked capacitor according to claim 1 . 9. The method according to claim 1, wherein the second amorphous silicon layer is formed under a reduced pressure C.
The method for manufacturing a stacked capacitor according to any one of claims 1 to 3 , wherein the deposition is performed at a temperature of less than 550 ° C and a thickness of 50 ° to 500 ° using a furnace for VD. 10. The method according to claim 1, wherein the second amorphous silicon layer has a thickness of less than 550.degree.
Deposited at a temperature of not less than 500 ° and mixed with hydrogen phosphide in silane or disilane, thereby being doped simultaneously with the deposition.
10 ²⁰ cm ^-3 or less preparation of a stack capacitor according to claim 1. 11. The method according to claim 1, wherein the HSG-like silicon layer is formed under a reduced pressure CV.
Using a furnace for D, at a temperature of 550 ° C. or more and 580 ° C. or less and a pressure of less than 1 Torr, the concentration in nitrogen is 1.0 × 1
Seeding with silane or disilane of 0 ^-3 mol · m ^-3 or less for 5 minutes or more and 120 minutes or less is performed under a condition of 550 ° C. or more and 580 ° C. or less in an atmosphere containing only nitrogen.
Claim 1 obtained by annealing within minutes
3. The method for manufacturing a stacked capacitor according to any one of 3 . 12. A silicon oxynitride-silicon oxide layer, wherein said silicon oxynitride-silicon oxide layer is formed by first subjecting an HSG-like silicon layer to a thermal oxidation treatment to a thickness of 10 to 60 mm. Forming a silicon dioxide layer, then forming a silicon nitride layer having a thickness of not less than 10 ° and not more than 60 ° on the silicon dioxide layer, and finally subjecting the silicon nitride layer to a thermal oxidation treatment to form a silicon oxynitride layer on the silicon dioxide layer; The method for producing a stacked capacitor according to claim 2 , wherein the method is obtained by forming a layer. 13. The method according to claim 1, wherein the upper electrode of the stacked capacitor has a thickness of 1000.degree.
3. The method according to claim 2 , wherein the polysilicon layer is obtained by depositing a polysilicon layer having a thickness of not more than 00 ° and performing an anisotropic reactive ion etching process using the photoresist pattern as a photomask and Cl2 as an etchant. A method for manufacturing the stacked capacitor described in the above. 14. The lower electrode structure according to claim 1, wherein said photoresist pattern is used as a photomask, and said HSG-like silicon layer and said first amorphous silicon layer are formed using Cl ₂ as an etching agent. 3. The method for manufacturing a stacked capacitor according to claim 2 , wherein the method is performed by performing patterning by an anisotropic reactive ion etching process. 15. The width of the fourth space between the lower electrode structure is 1000Å or 2000Å or less, the preparation of a stack capacitor of claim 2. 16. A pre-cleaning step under acidic conditions with diluted hydrofluoric acid is performed on the lower electrode base, and then the amorphous silicon layer is deposited and deposited in the same low pressure CVD furnace. By performing a seeding / annealing step, an HSG-like silicon layer is formed on the amorphous silicon layer. At this time, the amorphous silicon layer and the HSG-like silicon layer are both formed on the lower electrode base. Have been
A method for manufacturing a lower electrode structure for a stacked capacitor structure for a DRAM on a semiconductor substrate, comprising: a polysilicon gate structure formed on a gate insulating layer; and a source / drain formed in the semiconductor substrate. Providing a gate transistor comprising a region on the semiconductor substrate; depositing an insulating layer on the gate transistor; performing a planarization process on the insulating layer; Exposing a contact hole and exposing a surface of a source region in the gate transistor; depositing a first polysilicon layer on a surface of the insulating layer;
A step of completely filling the contact hole for the lower electrode; patterning the first polysilicon layer to form a polysilicon lower electrode base, and a first space between the polysilicon lower electrode bases. A pre-cleaning step performed under acidic conditions using the diluted hydrofluoric acid; in the furnace for reduced pressure CVD, on the polysilicon lower electrode base, and on the polysilicon lower layer. Depositing an amorphous silicon layer heavily doped with impurities on the first space including the side wall of the electrode structure to form a second space between the polysilicon lower electrode bases; In a furnace for use, an amorphous silicon layer doped with a small amount of impurities or an Depositing a silicon layer to form a third space between the polysilicon lower electrode bases; performing a seeding / annealing step in the low-pressure CVD furnace; Converting an amorphous silicon layer deposited on the crystalline silicon layer, doped with a small amount of impurities, or not doped with any impurities, into the HSG-like silicon layer; Forming a dielectric layer on the layer; depositing a second polysilicon layer on the dielectric layer; forming a photoresist pattern on the second polysilicon layer; Is used as a photomask to pattern the second polysilicon layer, and a stacked capacitor of the DRAM is used. Forming a silicon upper electrode; patterning the dielectric layer using the photoresist pattern as a photomask; and forming the HSG-like silicon layer using the photoresist pattern as a photomask. The amorphous silicon layer heavily doped with impurities is patterned to comprise the HSG-like silicon layer on the base of the lower polysilicon electrode and the amorphous silicon layer heavily doped with impurities. Forming a lower electrode structure and forming a fourth space between said polysilicon lower electrode structures. 17. The method according to claim 17, wherein the first polysilicon layer is formed by a low pressure CVD method at a temperature of 500.degree.
17. The method according to claim 16 , wherein the method is performed by depositing a mixture of silane or disilane with hydrogen arsenide or hydrogen phosphide, which is deposited at a temperature of 0 to 10,000, and doped simultaneously with the deposition. 18. The method according to claim 18, wherein said polysilicon lower electrode base is formed of Cl.
The method of claim 16, which is formed by anisotropic reactive ion _{etching 2} was etchant with respect to the first polysilicon layer. 19. The method according to claim 16 , wherein the width of the first space sandwiched between the polysilicon lower electrode bases is not less than 1500 ° and not more than 4000 °. 20. The pre-cleaning step, which is performed under acidic conditions using diluted hydrofluoric acid, comprises the step of preparing an acidic solution having a volume ratio of hydrogen fluoride to deionized water of 1: 100 to 200. 17. The method of claim 16 , implemented using. 21. The method of claim 19, wherein the amorphous silicon layer doped with a large amount of impurities is heated to a temperature of 55 ° C. by using the low pressure CVD furnace.
Deposited at 0 ° C. or more and 580 ° C. or less to a thickness of 50 ° or more and 1000 ° or less, and doped at the same time as depositing a mixture of silane and phosphorus, and having a surface impurity concentration of 4 × 10 ²⁰ cm ⁻³ or more. claims in the saturation level
Item 17. The method according to Item 16 . 22. The method according to claim 16 , wherein a width of the second space between the polysilicon lower electrode bases covered with the first amorphous silicon layer is not less than 1400 ° and not more than 3000 °. 23. A method according to claim 19, wherein the second amorphous silicon layer is formed by using the low pressure CVD furnace at a temperature of less than 550.degree.
Claims characterized by being deposited in the range of {over 500}
Item 17. The method according to Item 16 . 24. The method according to claim 24, wherein the second amorphous silicon layer is formed of the HS.
The seeding for converting to a G-like silicon layer /
The annealing step is performed using the furnace for low-pressure CVD, and the temperature is 550 ° C. or higher and 580 ° C. or lower, the pressure is lower than 1 Torr, and the concentration of silane in nitrogen is less than 1.0 × 10 ⁻³ mol · m ^−3. Or a seeding step performed using disilane for 5 minutes or more and 120 minutes or less, and an annealing step performed for 120 minutes or less under a condition of 550 ° C. or more and 580 ° C. or less in an atmosphere containing only nitrogen. Claims to be provided
The method according to item 16 , 25. The dielectric layer is composed of a silicon oxynitride layer-a silicon oxide layer, and the silicon oxynitride layer-a silicon oxide layer structure is formed on the HSG-like silicon layer by oxidizing with a thickness of 10 ° to 50 °. Depositing a silicon layer, then depositing a silicon nitride layer having a thickness of 10 to 60 degrees on the silicon oxide layer, and finally oxidizing the silicon nitride layer to form a silicon oxynitride layer on the silicon oxide 17. A method according to claim 16 obtained by: 26. The semiconductor device according to claim 26, wherein the second polysilicon layer is formed under a reduced pressure CV.
17. The method of claim 16 , wherein the method D is used to deposit at a temperature between 500C and 700C and a thickness between 500 and 2000C. 27. An anisotropic reactive ion etching step in which said polysilicon upper layer electrode is formed using said photoresist pattern as a photomask and said second polysilicon layer using Cl ₂ as an etchant. 17. The method of claim 16 , wherein the method is performed. 28. The HSG-like silicon layer and the amorphous silicon layer heavily doped with impurities are different from each other by using the photoresist pattern as a photomask and Cl ₂ as an etching agent. A lower electrode structure comprising the HSG-like silicon layer on the polysilicon lower electrode base and the heavily doped amorphous silicon layer patterned by performing an isotropic reactive ion etching process; Claim 1 which forms
7. The method according to 6 . 29. The width of the fourth space between the lower electrode structure is 1000Å or more 2000Å less claim 16
The method described in.