JPS622664A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to make a second oxide film thin, by providing a floating gate comprising polycrystalline silicon on a first insulating film, providing a second insulating film having high strength against an electric field only at the side wall surface of the floating gate, and providing a third insulating film, which covers the outer parts of the gate and the film. CONSTITUTION:A first gate oxide film 20 is formed on the surface of a substrate 10. A first gate (floating gate) 30 comprising a polycrystalline silicon film is formed on the film 20. A silicon nitride film 40 is formed on the side wall surface of the gate 30. A second gate oxide film 50 is formed around the gate 30 and the film 40. A second gate (control gate) 60 is formed on the film 50. The side wall surface of the floating gate is covered with the insulating film, whose strength against an electric field is sufficiently high. Therefore, electric charge in the floating gate is hard to escape even if a voltage is applied from the control gate. Even if the second gate oxide film is made thin, adverse effects are not imparted to keeping characteristics. Therefore, the second oxide film can be made thin without deteriorating keeping characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device and a method for manufacturing the same, and in particular is used in a SAMO8I EPROM having a control gate and a floating gate.

[Technical background of the invention]

SAMO8 (Stacke), which has a control gate and a floating gate, is a type of EPROM device.
d gate Avalanche 1njectio
Those having the n HO3) structure are known. ``This has a cell configuration as shown in FIGS. 3 to 5.

Figure 3 shows an erasable and programmable ROM (EP) with a SAMO3 structure.
ROM), FIG. 4 is a sectional view taken along line xx' in the figure, and FIG. 5 is a sectional view taken along line Y-Y' in FIG. 3.

According to these, a floating gate 3 is formed on a substrate 1 in an element region surrounded by a field oxide film 9 via a first gate insulating film 2, and a second gate insulating film 4 is formed on the floating gate 3.
A control gate 5 is formed through the gate, and a source region 7 and a drain region 8 are formed in the substrate around the gate. Such a configuration produces a memory effect by accumulating charge in the floating gate due to the avalanche phenomenon at the drain. Moreover, the avalanche voltage can be lowered by the control gate, and the writing speed can be improved.

In manufacturing such an EPROM, the second gate oxide film 4 is formed using polycrystalline silicon containing phosphorus as an impurity, and the floating gate 3 is formed by CVD deposition and patterning by reactive ion etching, and then thermal oxidation is performed. Generally, this floating gate is formed by oxidizing it.

This second gate oxide film is formed in a thickness of about 800 to 1200, and if the memory cell (floating gate) is charged with charge, there will be no problem in retaining the charge after that.

[Problems with background technology]

However, as miniaturization progresses, it has become necessary to make the second gate oxide film thinner in order to improve the write characteristics of EPROM devices. In this case, if the second gate oxide film is formed thinly using the conventional manufacturing method and charges are charged in the floating gate, the charged charges are controlled by the voltage (hereinafter referred to as V1) applied to the control gate during writing. A problem occurs in which the gate side can handle the problem (hereinafter referred to as a "keep failure").

This means that the electrical breakdown voltage of the second gate oxide film is 700 Å thick, as shown by the broken line in the graph of FIG.
This is because it decreases rapidly below.

As a method for improving the thermal oxide film breakdown voltage of polycrystalline silicon containing phosphorus even when the thickness is less than 700%, the phosphorus concentration in polycrystalline silicon is increased from 4 to 8×1020 CIIl.
-3 and the phosphorus diffusion temperature is proposed to be 900 to 950°C.

However, even this method is not a sufficient solution because the thickness of the second gate oxide film depends on the impurity concentration. In other words, the phosphorus concentration in the polycrystalline silicon that is the floating gate is high near the surface. Because it has a different concentration distribution in the depth direction, being lower on the substrate side,
Although the oxide film breakdown voltage on the upper part A1 of the floating gate electrode is improved, the problem remains that the oxide film breakdown voltage on the side wall side B of the floating gate is not always sufficiently improved. Therefore, the thickness of the second gate oxide film is 500 mm.
If it is less than Å, a keeping defect is still occurring.

[Purpose of the invention]

The present invention has been made in order to eliminate the above-mentioned drawbacks, and it is possible to improve the performance of the second gate oxide film of the EPROM device without deteriorating the ability to retain charge (hereinafter referred to as retention characteristic) in the 70-ring gate of the EPROM device. An object of the present invention is to provide a manufacturing method that can form an i-film into an i-film.

[Summary of the Invention] In order to achieve the above object, a semiconductor device according to the present invention includes a floating gate made of polycrystalline silicon containing impurities formed on a first insulating film, and a side wall surface of the floating gate. A second insulating film with high electric field strength is formed only on
An insulating film, and a method for manufacturing a semiconductor device according to the present invention includes a step of forming a first insulating film on a semiconductor substrate, and a step of forming a first gate on the first insulating film. A process of forming a polycrystalline silicon film to serve as an electrode, diffusing impurities into it, and then patterning it into a predetermined shape, forming a second insulating film with high electric field strength over the entire surface, and anisotropically a step of etching the polycrystalline silicon film so that only the side wall surface remains; a step of forming a third insulating film on the entire surface; and a step of forming a third insulating film on the polycrystalline silicon film. a step of forming a second gate electrode.

In the semiconductor memory device manufactured by such a method, the second gate I-oxide film can be made thinner without impairing the retention characteristics.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows cross-sectional views of the semiconductor memory device according to the present invention in each manufacturing process, and FIG. 1(f) shows the completed state.

According to FIG. 1(f), a first gate (floating gate) 30 made of a polycrystalline silicon film is formed on a first gate oxide film 20 formed on the surface of the substrate 10.
A silicon nitride film 40 is formed on the side wall surface of the silicon nitride film 40, and a second gate oxide film 50 is formed on the second gate oxide film 50 formed around the silicon nitride film 40.
It has a configuration in which a gate (control gate) 60 is formed.

Such a structure can be manufactured through the following steps.

First, a silicon substrate 10 is thermally oxidized to form a first gate oxide film 20, a polycrystalline silicon film is grown on this by, for example, a CVD method, and phosphorus is added to this film at a temperature of 900 to 950°C to a thickness of 4 to 8 x 1020 cm. The first gate 30 is implanted and diffused to a degree of −3 m and further patterned by reactive ion etching (RIE) to become a floating gate.
(Fig. 1(a)).

Next, as shown in FIG. 1(b), an insulating film 40 having a sufficiently large electric field strength is formed over the entire surface including the first gate 30. A silicon nitride film (Si3
There is N4).

When this insulating film 40 is then etched using reactive ion etching (RfE), the horizontal portions are removed and the insulating film 40 is formed only on the sidewalls of the first polycrystalline silicon layer 3o.
FIG.
It has a structure as shown in C).

After that, the second gate oxide film 50 is applied to the first polycrystalline silicon layer 3.
A second polycrystalline silicon layer 60, which is to become a control gate, is grown on the surface thereof by a CVD method or the like. Then, in order to process this control gate 60, a photoresist 70 is applied to obtain the structure shown in FIG. 1(e).

Next, the photoresist 70 is exposed, developed and patterned, and the second polycrystalline silicon layer 60 is formed by RIE.
Second gate oxide film 50 and first polycrystalline silicon layer 30
A gate and wiring are formed in a predetermined shape by etching to complete a memory cell as shown in FIG. 1(f).

In this way, in the manufacturing method according to the present invention, after processing the polycrystalline silicon layer containing phosphorus, which will become the floating gate 1 electrode, an insulating film such as a nitride film with sufficiently high electric field strength is formed on the side walls of the floating gate electrode. The second
It is formed by thermally oxidizing the gate oxide film.

FIG. 2 is a characteristic diagram showing the relationship between the second gate oxide film breakdown voltage and the WX2 gate oxide film thickness of a typical EFROM device.

As is clear from this characteristic diagram, when there is no nitride film on the sidewalls of the floating gate, the second gate oxide film has a thickness of 600
When the voltage drops below Å, the withstand voltage (MV/
c/I) decreases, but the degree of decrease is small when a nitride film is formed on the sidewalls, and the second gate oxide film thickness is 40%.
It can be seen that practical use is possible even if the value is 0.8 or less.

In the above embodiments, the insulating film formed on the side wall of the first gate was a silicon nitride film, but it may be any material as long as it has a high electric field strength, and for example, a glass film such as BSG may be used. can.

Further, the second gate oxide film may be formed by thermal oxidation as in the embodiment, or a silicon nitride film may be formed by CVD.

〔Effect of the invention〕

As described above in detail based on the embodiments, according to the semiconductor memory device according to the present invention, the side wall surface of the 70-ring gate is covered with an insulating film having a sufficiently large electric field strength, so that the charge inside the floating gate is controlled. It is difficult to escape even when voltage is applied to the gate, and is maintained even if the second gate oxide film is thinned.

Since the characteristics are not adversely affected, the second gate oxide film can be made thinner without causing a keep failure.

Further, according to the method of manufacturing a semiconductor memory device according to the present invention, after the first gate is formed, an insulating film having a high electric field strength is formed on the entire surface of the first gate, and is anisotropically etched so that only the side wall portion remains. Therefore, it is possible to reliably use the semiconductor memory device described above.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an element according to each step to explain an embodiment of the present invention, and FIG. 2 shows the thickness of the second gate oxide film and the thickness of the second gate oxide film depending on the presence or absence of a nitride film on the side wall of a 70-ring gate. A characteristic diagram showing the relationship with membrane breakdown voltage, Figure 3 is E'PR
A plan view showing the structure of the OM device, and FIGS. 4 and 5 are cross-sectional views thereof. 1.10... Semiconductor substrate, 2,2o... First gate oxide film, 3.30... First polycrystalline silicon layer (floating gate), 40... Insulating film, 4,50...・
2nd game 1~oxide film, 5, 60...second polycrystalline silicon li! (control gate), 6.70...photoresist. 2nd floor, Wanhou, 2nd garden, Figure 3, Figure 3

Claims (1)

[Claims] 1. A floating gate made of impurity-containing polycrystalline silicon formed on a first insulating film, and a second insulating film having a high electric field strength and formed only on the side wall surface of the floating gate. A semiconductor memory device comprising: a film; and a third insulating film surrounding the film. 2. The semiconductor memory device according to claim 1, wherein the second insulating film is a silicon nitride film. 3. The semiconductor memory device according to claim 1 or 2, which has a control gate on the third insulating film. 4. Forming a first insulating film on the semiconductor substrate; forming a polycrystalline silicon film that will become the first gate electrode on the first insulating film, and diffusing impurities into this; a step of forming a second insulating film with high electric field strength on the entire surface and etching it by anisotropic etching so that only the side wall surface of the polycrystalline silicon film remains. A method for manufacturing a semiconductor memory device, comprising: forming a third insulating film over the entire surface; and forming a second gate electrode on the third insulating film above the polycrystalline silicon film. . 5. The semiconductor memory device and its manufacturing method according to claim 4, wherein the second insulating film is a silicon nitride film formed by a CVD method. 6. The semiconductor memory device and its manufacturing method according to claim 4, wherein the first insulating film and the second insulating film are silicon oxide films formed by thermal oxidation. 7. The method of manufacturing a semiconductor memory device according to claim 4, wherein the anisotropic etching is reactive ion etching.