JPH0358179B2 - - Google Patents
Info
- Publication number
- JPH0358179B2 JPH0358179B2 JP56154608A JP15460881A JPH0358179B2 JP H0358179 B2 JPH0358179 B2 JP H0358179B2 JP 56154608 A JP56154608 A JP 56154608A JP 15460881 A JP15460881 A JP 15460881A JP H0358179 B2 JPH0358179 B2 JP H0358179B2
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- film
- groove
- grooves
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 239000012212 insulator Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 2
- 238000002955 isolation Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 241000293849 Cordylanthus Species 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 206010040844 Skin exfoliation Diseases 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体集積回路（IC）の素子間分離
（アイソレーシヨン）の形成方法、特に深くて幅
の狭い溝を有する溝型アイソレーシヨンの形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming isolation between elements of a semiconductor integrated circuit (IC), and particularly to a method for forming trench type isolation having deep and narrow trenches.
半導体ICの集積度を上げる一つの要素として、
アイソレーシヨンをいかに完全に形成するかとい
うことが挙げられる。すなわち、絶縁が完全であ
り、耐圧が高く、分離容量の小さいアイソレーシ
ヨンの形成が望まれているわけであるが、最近の
高集積度化傾向に相まつて、深くて幅の狭い溝を
有するアイソレーシヨンの形成が要求される事例
が多いが、それに関連して種々の問題が発生して
きている。 As one of the factors to increase the degree of integration of semiconductor ICs,
One issue is how to form isolation completely. In other words, it is desired to form an isolation device with perfect insulation, high withstand voltage, and small isolation capacitance. Although there are many cases where formation of isolation is required, various problems have arisen in connection with this.
例えば、選択酸化を利用してMOS ICを製造す
る際のLOCOS法においては、第１図に示すよう
に、シリコン基板１上に厚いシリコン酸化膜２を
形成する場合、高温長時の熱処理を要し、いわゆ
る鳥の口ばし（Bird′s beak）３が形成され、こ
の部分だけ余分な面積をとることとなり、結果的
に微細化が困難となる。なお、同図中２′はゲー
ト酸化膜（二酸化シリコン）を表わす。また、ポ
イポーラトランジスタの製造においてPN接合分
離を行う場合、P+不純物拡散層は横方向の拡が
りをともないやはり高集積度化には不適である。
さらには、第２図に示すように、シリコン基板５
に略垂直に深い溝を形成し、そこにシリコン酸化
物を化学気相成長法（CVD法）で充填しようと
すると、幅の狭い溝６においてはシリコン酸化物
が７，７′……と成長ゆるにしたがい入口付近が
封鎖され、溝内部に空洞（鬆）８が形成されると
いう問題が発生する。また、溝幅が異る場合に
は、狭い溝６が充填されても、広い溝６′は、ま
だ埋まらないということが起こる。つまり、充填
に必要な膜厚が溝幅依存性を有するという問題が
ある。 For example, in the LOCOS method when manufacturing MOS ICs using selective oxidation, as shown in Figure 1, when forming a thick silicon oxide film 2 on a silicon substrate 1, heat treatment at high temperature and for a long time is required. However, a so-called bird's beak 3 is formed, which requires an extra area, and as a result, miniaturization becomes difficult. Note that 2' in the figure represents a gate oxide film (silicon dioxide). Further, when PN junction isolation is performed in the manufacture of a popolar transistor, the P + impurity diffusion layer expands in the lateral direction, which is still unsuitable for high integration.
Furthermore, as shown in FIG.
When a deep groove is formed almost perpendicular to the groove 6 and silicon oxide is filled therein by chemical vapor deposition (CVD), silicon oxide grows in the narrow groove 6 in the order of 7, 7', etc. As the groove becomes looser, the vicinity of the entrance is closed off, creating a problem in that a cavity 8 is formed inside the groove. Further, when the groove widths are different, even if the narrow groove 6 is filled, the wide groove 6' may not be filled yet. In other words, there is a problem in that the film thickness required for filling depends on the groove width.
本発明は上記従来技術の課題を解決すべく、そ
のために溝内への絶縁物の充填を垂直蒸着を利用
して行い。合わせてホトレジスト膜又は、ポリイ
ミド膜等の形成とそれのエツチングとを適宜組み
合わせて、従来の技術にみられる欠点のないアイ
ソレーシヨンを形成することができる方法を提供
するものであり、これにより高集積度化がいつそ
う改善されるものである。すなわち、半導体基板
上に、開口部を有する第１のレジスト膜を形成す
る工程と、該第１のレジスト膜をマスクとして、
半導体基板に略垂直に溝を形成する工程、該溝内
に垂直蒸着で絶縁物を、その上面が前記第１のレ
ジスト膜の上面を超えないように充填する工程、
前記溝内に絶縁物をおおい、かつ、前記第１のレ
ジスト膜と接続する第２のレジスト膜を形成し、
前記第１のレジスト膜と第２のレジスト膜によつ
て溝内の絶縁物を密閉する工程、前記溝の外部の
絶縁物を選択的に除去する工程を含むことを特徴
とする半導体装置の製造方法を提供するものであ
る。 In order to solve the above-mentioned problems of the prior art, the present invention fills the trench with an insulating material using vertical vapor deposition. In addition, the present invention provides a method that can appropriately combine the formation of a photoresist film or a polyimide film, etc., and its etching to form isolation without the drawbacks seen in conventional techniques. The degree of integration will be improved over time. That is, a step of forming a first resist film having an opening on a semiconductor substrate, and using the first resist film as a mask,
a step of forming a substantially perpendicular groove in the semiconductor substrate; a step of filling the groove with an insulator by vertical vapor deposition so that the upper surface thereof does not exceed the upper surface of the first resist film;
covering the groove with an insulator and forming a second resist film connected to the first resist film;
Manufacturing a semiconductor device, comprising the steps of: sealing an insulator in a trench with the first resist film and a second resist film; and selectively removing an insulator outside the trench. The present invention provides a method.
以下、本発明の実施例を添付図面にもとづいて
説明する。 Embodiments of the present invention will be described below with reference to the accompanying drawings.
第３図ないし第５図は本発明にかゝるアイソレ
ーシヨンの製造工程における要部の断面図であ
る。先ず第３図に示すように、シリコン基板１１
に形成された第１のホトレジスト膜１３をパター
ニングし、ドライプロセスのイオンエツチングに
より又は、ウエツトエツチではやゝオーバーエツ
チにし、略垂直に深い溝１２，１２′を1μｍの深
さに掘り、そのまゝの状態でシリコン酸化膜
（SiO2）１４，１４′を1μｍの厚さに垂直蒸着す
る。これにより、溝１２，１２′内とホストレジ
スト膜１３が残存する平坦部上には同じ厚さに酸
化膜１４，１４′が形成されるが、溝内に堆積し
た酸化膜１４をみると、溝が余り垂直であるとそ
の表面周辺部においてシリコン基板１１とわずか
に段差が生ずる場合がある。（段差を減らすには、
溝壁の垂直からの角度が30°〜40°がよい）続い
て、第４図に示すように、第２のホトレジスト膜
５をスピンコート法（基板を回転しながらレジス
ト液を滴下して回転塗布する）により、図に点線
で示す位置まで塗布し、しかる後に実線で示す位
置、すなわち平坦部上に堆積した酸化膜１４′の
表面が露出する位置まで現像処理により除去す
る。（エツチング）。なお、ホトレジストの代わり
にポリイミド等を使用してもよく、ホトレジスト
膜ポリイミド膜の除去は現像に代えて灰化を利用
してもよい。次に、前記のように形成した第１の
ホトレジスト膜１３と第２のホトレジスト膜１５
を保護膜としてエツチングにより露出している酸
化膜１４′を除去し、次いでホトレジスト膜１３
と１５のはく離を行う。 3 to 5 are cross-sectional views of main parts in the manufacturing process of the isolation according to the present invention. First, as shown in FIG.
The first photoresist film 13 formed on the photoresist film 13 is patterned, and deep grooves 12 and 12' are dug approximately vertically to a depth of 1 μm by ion etching in a dry process or slightly overetched by wet etching. Under these conditions, silicon oxide films (SiO 2 ) 14, 14' are vertically deposited to a thickness of 1 μm. As a result, oxide films 14 and 14' are formed with the same thickness in the grooves 12 and 12' and on the flat portion where the host resist film 13 remains, but when looking at the oxide film 14 deposited in the grooves, If the groove is too perpendicular, a slight difference in level from the silicon substrate 11 may occur at the periphery of the surface. (To reduce the level difference,
The angle of the groove wall from the vertical is preferably 30° to 40°.) Next, as shown in FIG. The oxide film 14' is coated to the position shown by the dotted line in the figure, and then removed by development processing to the position shown by the solid line, that is, the position where the surface of the oxide film 14' deposited on the flat portion is exposed. (Etching). Note that polyimide or the like may be used instead of photoresist, and ashing may be used instead of development to remove the photoresist film and polyimide film. Next, the first photoresist film 13 and the second photoresist film 15 formed as described above are
The exposed oxide film 14' is removed by etching using the photoresist film 13 as a protective film.
and 15 peelings are performed.
最後に、第５図に示すように、溝内の酸化膜１
４の表面周辺部とシリコン基板１１との段差を無
くして平坦化する目的で、全面いSiO2の膜１７
を熱酸化、スパツタリングあるいはCVD法によ
り成長させ、続いてエツチングにより上表面の
SiO2を除去してシリコン基板を露出させる。な
お、上表面のSiO2１７を形成するには、一度
CVD法により多結晶シリコン（ポリシリコン）
お成長させ、またはスパツタリング法により非晶
質シリコン（アモルフアスシリコン）を成長さ
せ、次にそれらを酸化する方法によつてもよい。
さらには、溝内のSiO2１４に不純物、例えばホ
ウ素（B+）をドーピングし、熱処理を行いP+導
電型のチヤンネルカツト領域（図中点線部分）を
形成することもできる。 Finally, as shown in FIG.
In order to eliminate the level difference between the peripheral part of the surface of 4 and the silicon substrate 11 and flatten it, a thick SiO 2 film 17 is formed on the entire surface.
is grown by thermal oxidation, sputtering or CVD, and then etched to form the top surface.
Remove SiO 2 to expose the silicon substrate. Note that in order to form SiO 2 17 on the upper surface,
Polycrystalline silicon (polysilicon) made by CVD method
Alternatively, amorphous silicon may be grown by a sputtering method, and then oxidized.
Furthermore, it is also possible to dope the SiO 2 14 in the groove with an impurity, such as boron (B + ), and perform heat treatment to form a P + conductivity type channel cut region (the dotted line portion in the figure).
なお、前記最終工程は、半導体IC製造の全工
程の中で、次工程において特に必要と認められな
い場合には省略することができるものである。 Note that the final step can be omitted if it is not deemed particularly necessary in the next step among all the steps of semiconductor IC manufacturing.
以上本発明は、(1)イオンエツチング法等で略垂
直に深い溝を掘る工程、(2)垂直蒸着で溝内に
SiO2を充填する工程、および(3)溝内のSiO2上に
選択的にホトレジスト膜を形成し、これを保護膜
として余分のSiO2を除去した後に、ホトレジス
ト膜をはく離して溝内のSiO2のみを残す工程を
組み合せてアイソレーシヨンを形成するので、従
来技術にみられた鳥の口ばしや鬆などの欠陥が防
止でき、微細化に適したアイソレーシヨンの製造
方法が実現されるものである。 As described above, the present invention includes (1) a step of digging a deep groove substantially vertically using an ion etching method, etc.;
Step of filling SiO 2 and (3) selectively forming a photoresist film on the SiO 2 in the trench, using this as a protective film to remove excess SiO 2 , and then peeling off the photoresist film to fill the inside of the trench. Since isolation is formed by combining processes that leave only SiO 2 , it is possible to prevent defects such as bird's beaks and mandrels that are seen in conventional technology, creating an isolation manufacturing method suitable for miniaturization. It is something that will be done.
また、始めのホトレジスト１３を、スペーサ
（後に除去する）として残したまま、基板１１表
面にPSG、Si2N4、Al等を成長し、基板と共にパ
ターニングするので溝上の残存レジスト１５の厚
さが増し、歩留が向上する。絶縁物としては、
SiO2に限らず、SiO、SixOyNz、Al2O3等を使用
することができる。 In addition, PSG, Si 2 N 4 , Al, etc. are grown on the surface of the substrate 11 while leaving the initial photoresist 13 as a spacer (to be removed later) and patterned together with the substrate, so that the thickness of the remaining resist 15 on the groove is reduced. This increases the yield. As an insulator,
Not limited to SiO 2 , SiO, Si x O y N z , Al 2 O 3 , etc. can be used.
第１図はLOCOS法によるアイソレーシヨン形
成工程を示す断面図、第２図はCVD法により溝
内SiO2を形成するときの状態を示す断面図、第
３図ないし第５図は本発明にかかるアイソレーシ
ヨン形成の製造工程におけるその要部の断面図で
ある。
１，５，１１……シリコン基板、２，２′，７，
７′，１４，１４′，１７……SiO2膜、３……鳥
の口ばし、６，６′，１２，１２′……溝、８……
鬆、１３，１５……ホトレジスト膜。
Fig. 1 is a cross-sectional view showing the isolation forming process by the LOCOS method, Fig. 2 is a cross-sectional view showing the state when forming SiO 2 in the groove by the CVD method, and Figs. FIG. 3 is a cross-sectional view of the main part in the manufacturing process of forming such isolation. 1, 5, 11...Silicon substrate, 2, 2', 7,
7', 14, 14', 17... SiO 2 film, 3... Bird's beak, 6, 6', 12, 12'... Groove, 8...
13, 15...Photoresist film.
Claims (1)
レジスト膜１３を形成する工程と、 該第１のレジスト膜１３をマスクとして、半導
体基板１１に略垂直に溝１２，１２′を形成する
工程、 該溝１２，１２′内に垂直蒸着で絶縁物１４を、
その上面が前記第１のレジスト膜１３の上面を超
えないように充填する工程、 前記溝１２，１２′内の絶縁物をおおい、かつ、
前記第１のレジスト膜１３と接続する第２のレジ
スト膜１５を形成し、前記第１のレジスト膜１３
と第２のレジスト膜１５によつて溝１２，１２′
内の絶縁物を密閉する工程、 前記溝１２，１２′の外部の絶縁物１４′を選択
的に除去する工程を含むことを特徴とする半導体
装置の製造方法。[Claims] 1. A step of forming a first resist film 13 having an opening on the semiconductor substrate 11, and using the first resist film 13 as a mask, forming grooves 12, substantially perpendicularly to the semiconductor substrate 11. 12', an insulator 14 is vertically deposited in the grooves 12, 12',
a step of filling the resist film so that its upper surface does not exceed the upper surface of the first resist film 13; covering the insulator in the grooves 12, 12'; and
A second resist film 15 connected to the first resist film 13 is formed, and the second resist film 15 is connected to the first resist film 13.
and the grooves 12, 12' by the second resist film 15.
A method for manufacturing a semiconductor device, comprising the steps of: sealing an insulator inside the grooves 12, 12'; and selectively removing an insulator 14' outside the grooves 12, 12'.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15460881A JPS5856353A (en) | 1981-09-29 | 1981-09-29 | Forming method for isolation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15460881A JPS5856353A (en) | 1981-09-29 | 1981-09-29 | Forming method for isolation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5856353A JPS5856353A (en) | 1983-04-04 |
| JPH0358179B2 true JPH0358179B2 (en) | 1991-09-04 |
Family
ID=15587895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15460881A Granted JPS5856353A (en) | 1981-09-29 | 1981-09-29 | Forming method for isolation |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856353A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5192706A (en) * | 1990-08-30 | 1993-03-09 | Texas Instruments Incorporated | Method for semiconductor isolation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108773A (en) * | 1977-03-04 | 1978-09-21 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
-
1981
- 1981-09-29 JP JP15460881A patent/JPS5856353A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108773A (en) * | 1977-03-04 | 1978-09-21 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5856353A (en) | 1983-04-04 |
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