JP2000022153A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method capable of forming a minute pattern. SOLUTION: A semiconductor device is constituted of a groove with a two- step tapered angle formed on a semiconductor substrate, a thermal oxide film formed on the side and the bottom of the groove, a thermal oxide sidewall 8 filling the groove and a CVD oxide film 11, a gate oxide film 12 overlaid on the thermal oxide sidewall 8 and the CVD oxide film 11, and a gate polysilicon 13 overlaid thereon. In this structure, an upper edge of the trench is protected by the thermal oxide sidewall 8 from the gate polysilicon 13. In this case, the thermal oxide film formed in a thermal oxidizing step remains until the trench separation is completely formed, so that the amount of retreat for the oxide film at the top of the trench in a oxide-film wet-etching step can be reduced to minimum. At the same time, a reverse narrow channel effect of an MOS transistor can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device and a method of manufacturing the semiconductor device, a method of forming an element isolation region is mainly a method of forming an LO.
The COS method is used. However, in the LOCOS method, the size conversion difference due to bird's beak is large. For this reason,
It is difficult to miniaturize the element, which hinders high density of the element. Therefore, in recent years, studies have been made on a trench isolation method for embedding an insulating film for element isolation in a groove. According to this method, the minimum separation width between elements can be made 0.2 μm or less, so that high-density LSI can be manufactured.

However, it is known that such a trench isolation method has the following problems. FIG. 3 is a characteristic diagram showing a relationship between a threshold value Vt and a channel width W of an NMOS transistor using trench isolation for element isolation. In FIG. 3, it is known that the threshold value Vt decreases as the channel width W decreases. In particular, when the channel width W is less than 0.5 μm, it can be seen that this decrease is remarkable. Therefore, in the case of a transistor having a channel width of 0.5 μm or less, problems such as the transistor not being turned off or the variation in the threshold value Vt increasing. For this reason, this technology cannot be practically applied to devices. This phenomenon is generally called an inverse narrow channel effect, and is a major obstacle in applying trench isolation to devices.

It is known that this phenomenon is caused by the shape of the upper end of the trench isolation. Hereinafter, this content will be described using the schematic diagram of FIG. FIG. 4A is a cross-sectional view of the trench isolation after the formation of the gate polycide electrode, and FIG. 4B is an enlarged view of the dotted line in the figure. Si substrate 2
1 is buried by a thermal oxide film 27 and a CVD oxide film 31 formed on the side and bottom surfaces thereof, and a gate oxide film 32, a gate polysilicon 33, and a tungsten silicide 34 are formed thereon. A MOS transistor having a gate polycide electrode is formed. When a voltage is applied to this gate electrode, an electric field concentrates on a sharp portion (dotted line portion in FIG. 4B) at the upper end of the trench isolation, and the gate voltage effectively applied to the trench end becomes apparently higher and becomes flat. The channel is formed earlier than the part. That is, a transistor having a lower threshold value Vt than the flat portion is formed at the trench end.

In such a transistor, as the channel width W becomes narrower, the ratio of the channel width at the trench end to the whole channel width increases, and finally, when the channel width W <0.5 μm, The threshold value is determined only by the transistors. Therefore, the dependence of the threshold value Vt on the channel width W occurs as shown in FIG.

As described above, the above problem is caused by the concentration of the electric field at the sharp portion at the upper end of the trench. To solve this, the following method has been proposed. In JP-A-63-2371, this is avoided by giving a curvature to the silicon substrate at the upper end of the trench. Hereinafter, with reference to the process cross-sectional views of FIGS.
The configuration and manufacturing method will be described.

First, a pad oxide film 22 is formed on a Si substrate 21.
And a nitride film 23, and a photolithography technique,
Then, this laminated structure is patterned by an etching technique to obtain a structure shown in FIG. Next, the first groove 24 is formed by etching the Si substrate 21 using the nitride film 23 as a mask (FIG. 5B), and then subjected to thermal oxidation in a 1000 ° C. wet atmosphere to form a side surface of the first groove 24. Then, a thermal oxide film 30 is formed on the bottom surface (FIG. 5C). Due to this oxidation, the upper end of the trench is oxidized to have a curvature. Next, a part of the first groove 24 that has not been filled by the oxidation is completely buried with the CVD oxide film 31 (FIG. 5).
(D)) extra CVD deposited on the active area
The oxide film 231 is removed by anisotropic etching or chemical mechanical polishing (CMP) to obtain a structure shown in FIG.

Thereafter, the nitride film 23 and the pad oxide film 22 are removed by isotropic etching (FIG. 5F). Finally, the Si substrate 21 is oxidized (not shown), ion-implanted to adjust the threshold value of the transistor, and then removed by isotropic etching to form the gate oxide film 3
2. A gate polysilicon 33 and a tungsten silicide 34 are sequentially formed to obtain a structure shown in FIG. According to this method, the side surface after the trench etching is oxidized at a high temperature so that the shape of the upper end portion of the trench has a curvature, thereby preventing electric field concentration when a gate voltage is applied, and thereby suppressing a decrease in the threshold value of the transistor. be able to.

In the same proposal, the following method is also given as a method of giving a curvature to the upper portion of the trench.
Hereinafter, a method according to the cross-sectional process diagrams of FIGS. 6A to 6H will be described.

FIG. 6A shows a state after a pad oxide film 22 and a nitride film 23 are deposited on a Si substrate 21 and this laminated structure is patterned using photolithography and etching techniques. Next, wet etching,
For example, if the mixing ratio is hydrofluoric acid: nitric acid: glacial acetic acid = 10: 1: 3
The first groove 24 is formed by etching the pad oxide film 22 and the Si substrate 21 using the solution No. 00 (FIG. 6).
(B)). By this etching, the pad oxide film 22 recedes and the Si substrate 21 is gently etched, so that the edge of the Si substrate 21 has a curvature. Thereafter, a second groove 29 is formed by anisotropic etching using the nitride film 23 as a mask (FIG. 6C), and a thermal oxide film 27 is formed on the side and bottom surfaces of the groove 9 by thermal oxidation. 6 (d) is obtained. Next, the CVD oxide film 31
The trench 29 is completely buried (FIG. 6E), and the excessive thermal oxide film 27 deposited on the nitride film 23 is removed by anisotropic etching or CMP (FIG. 6F). The nitride film 23 and the pad oxide film 22 are removed by isotropic etching (FIG. 6G).

Finally, thermal oxidation, threshold adjustment ion implantation, and wet etching of an oxide film are performed to form a gate electrode, thereby obtaining the structure shown in FIG. 6 (h). According to this method, by using both wet etching and anisotropic etching and providing the groove 29 with a two-step inclination angle (taper angle), the upper end of the trench can have a curvature. Therefore, a decrease in the threshold value of the MOS transistor due to a decrease in the channel width can be suppressed.

A method of manufacturing a trench isolation having a two-step taper angle has been proposed in Japanese Patent Application Laid-Open No. 58-131747, entitled "Method of Manufacturing Semiconductor Device". Hereinafter, the manufacturing method will be described with reference to FIGS.

First, a pad oxide film 22 is formed on a Si substrate 21.
And a nitride film 23, and a photolithography technique,
Then, this laminated structure is patterned by an etching technique to obtain a structure shown in FIG. Next, the exposed Si substrate 21 is etched using the nitride film 23 as a mask to form a first groove 24 having a tapered side surface (FIG. 7).
(B)). Next, after an oxide film is deposited on the entire surface of the wafer by a CVD method (not shown), anisotropic etching is performed until the nitride film 23 is exposed. As a result, oxide film sidewalls 35 are formed on the side surfaces of the nitride film 23, the pad oxide film 22, and the first groove 24 (FIG. 7C). Next, using the nitride film 23 and the oxide film sidewall 35 as a mask, a vertical second groove 29 is formed by anisotropic etching (FIG. 7D), and isotropic oxide film etching is further performed. The oxide film sidewall 35 is removed to obtain the structure shown in FIG. Thereafter, the second groove 29 is completely buried with the CDV oxide film 31 formed by the CVD method (FIG. 7F), and is planarized by anisotropic etchback or CMP (FIG. 7G). After removing the nitride film 23 and the pad oxide film 22 by isotropic etching (FIG. 7 (h)), thermal oxidation, ion implantation for adjusting the threshold value, wet etching of the oxide film, and formation of the gate electrode, FIG. The structure shown in FIG.

According to this method, after forming the first groove 24 having a taper, the vertical second groove 29 can be formed by using the oxide film sidewall 35 as an etching mask. Thus, a trench isolation having a two-stage taper angle can be realized.

[0015]

However, even with the trench isolation formed by the above method, there is a problem that the electric field concentration at the upper end of the trench cannot be sufficiently reduced. That is, even when the substrate shape at the upper end portion of the trench is given a curvature by the above method, as shown in the trench isolation sectional view of FIG. A buried oxide film called “divot” is formed at the upper end. Here is the gate polysilicon 33
Is deposited so as to surround the upper end of the trench. For this reason, it is not possible to avoid a problem that a concentrated electric field, that is, a concentration of electric charges occurs. This is because the wet etching rate of the CVD oxide film used to completely bury the trench is higher than that of the thermal oxide film, so that the oxide film at the upper end of the trench is easily lost, and therefore the upper end of the trench is easily exposed. Is due.

Further, a CVD oxide film 3 for burying the trench is provided.
1, when using bias ECRCVD in which sputter etching and deposition are performed simultaneously, according to the conventional trench isolation formation method, the oxide film formed on the upper end of the trench is thin, and the Si substrate is damaged. Also, there is a problem that the junction leakage characteristics are easily deteriorated.

Further, when the trench side surface is oxidized at a high temperature of 1000 ° C. or more to give a curvature to the upper end portion of the trench, a wafer warp or a slip dislocation occurs, and lithography of a fine pattern and a junction leak characteristic are deteriorated. It has been pointed out that it has an adverse effect.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a semiconductor device and a method of manufacturing a semiconductor device which enable fine patterning.

More specifically, the present invention reduces the etching rate of the buried oxide film at the upper end of the trench isolation, prevents the substrate corner from being exposed, and reduces the taper angle of the trench by two.
It is an object of the present invention to provide a semiconductor device having no inverse narrow channel effect and a method for manufacturing the semiconductor device by forming a step.

[0020]

In order to achieve the above object, a semiconductor device according to the first aspect of the present invention comprises a groove formed on a semiconductor substrate and having a two-stage taper angle, and side and bottom surfaces of the groove. Thermal oxide film formed on the substrate, a thermal oxide film sidewall and a CVD oxide film buried in the trench, a gate oxide film, and a gate further covering the gate oxide film, the thermal oxide film sidewall and the CVD oxide film Polysilicon and the upper end of the trench is protected from the gate polysilicon by the sidewall of the thermal oxide film.

Further, by forming the above-mentioned two-stage taper angle in the groove, concentration of electric charges on the corner of the groove can be avoided, and the semiconductor device is constituted by further covering the gate polysilicon with tungsten silicide. The substrate may be a silicon substrate.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a pad oxide film by oxidizing a surface of a semiconductor substrate; and forming a buried oxide film on the pad oxide film. A step of depositing a film functioning as a stopper at the time of planarization, a step of forming an opening by processing by photolithography and dry etching, a step of forming a first groove (trench) (4) having a taper, and a first step. Forming a thermal oxide film (5) by thermal oxidation on the side and bottom surfaces of the groove (4), depositing polysilicon (6) over the entire surface of the wafer by LPCVD, and thermally oxidizing the polysilicon. A step of forming a thermal oxide film, and etching back the thermal oxide film (7) by anisotropic etching to expose the semiconductor substrate (1) and the stopper layer; Ri formed thermal oxide film sidewall (8) and a step of forming the trench upper end portion.

Further, a step of vertically forming a second groove (9) using the stopper layer and the side wall of the thermal oxide film (8) as a mask, and thermally oxidizing the side and bottom surfaces of the second groove (9). A step of forming a thermal oxide film (10), a step of embedding the first groove and the second groove with a CVD oxide film (11), and a step of depositing a CVD oxide film on the stopper layer until the stopper layer is exposed ( 11) removing the stopper layer (3) and the pad oxide film (2) by isotropic etching such as wet etching in which the thermal oxide film sidewall (8) is also slightly etched; Performing a threshold adjustment ion implantation with a sacrificial oxide film through formed by thermal oxidation.

Further, the above-described method for manufacturing a semiconductor device comprises:
A step of sequentially depositing a gate oxide film (12), a gate polysilicon (13), and a tungsten silicide (14) after the ion implantation, and a film functioning as a stopper when the buried oxide film is planarized is a nitride film (23). The removal of the CVD oxide film (11) may be performed by CMP or dry etching.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention.

Hereinafter, an embodiment of the trench isolation forming method according to the present invention will be described with reference to the process sectional views of FIGS. 1 (a) to 1 (k).

In the present embodiment, a silicon substrate 1 is used as the semiconductor substrate 1, a groove is formed in the silicon substrate 1, and the groove is formed and buried with a CVD oxide film. Note that the present invention can be applied to any semiconductor device that uses trench isolation for element isolation.

First, a first insulator layer, preferably a pad oxide film 2, is formed on a Si substrate 1. Pad oxide film 2
Has a thickness of 5 to 20 nm for the purpose of alleviating the stress generated in the subsequent processing steps. Subsequently, a second insulator layer, preferably a nitride film 3 is formed on the pad oxide film 2.
To form The nitride film 3 functions as a stopper layer at the time of planarizing the buried oxide film, and the film thickness is preferably as thin as possible within a range where polishing or etching does not reach the substrate during planarization by CMP or the like. 100-30
It has a thickness of 0 nm. Here, on the nitride film 3, for example, a photoresist having a thickness of 1μm was applied (not shown), forming an isolation pattern by photolithography, which the mask, different using, for example, CF ₄ gas Nitride film 3 by anisotropic reactive ion etching,
The pad oxide film 2 is sequentially etched to form the silicon substrate 1
To expose. As a result, desired element isolation patterns having various element isolation widths and active area widths are formed. The element isolation width and the active area width vary depending on the degree of integration of the element, but are about 0.1 to 100 μm. Next, the photoresist is removed to obtain a structure shown in FIG.

Next, the nitride film 3 as a mask, for example, HB _r
The silicon substrate 1 is anisotropically etched using a mixed gas of O ₂ and O ₂ to form a first groove 4 having a taper angle of, for example, 10
0 nm is formed. Further, the silicon substrate 1 is thermally oxidized in a dry atmosphere at, for example, 900 ° C. using the nitride film 3 as an oxidation-resistant mask, and a third insulating film, preferably a thermal oxide film, is formed on the side walls and the bottom surface of the first groove 4. 5 is formed. The thermal oxide film 5 functions as a layer for removing damage when the first groove 4 is etched.
10 to 50 nm is appropriate. In the present embodiment,
Although the first groove 4 is etched using the nitride film 3 as a mask, the same effect can be obtained by etching the groove 4 before removing the photoresist (FIG. 1B).

Next, the polysilicon 6 is formed by the LPCVD method.
Is deposited on the entire surface of the wafer. At this time, it is important that the thickness of the polysilicon is not more than 1/4 of the minimum separation width in the device, and for example, 10 to 50 nm is appropriate (FIG. 1C).

Next, thermal oxidation is performed to completely oxidize the polysilicon deposited in the previous step to form a thermal oxide film 7.
At this time, the polysilicon reacts with oxygen to form 2.
The polysilicon thickness needs to be selected so that the trench with the minimum separation width is not completely buried by this thermal oxidation, since it expands to twice the deposition. Therefore, the thickness of the polysilicon to be deposited must be equal to or less than 1/4 of the minimum separation width as described above (FIG. 1D).

Subsequently, the thermal oxide film 7 is etched by anisotropic etching until the nitride film 3 and the Si substrate 1 are exposed. As an etching gas, for example, a mixed gas of CF ₄ and O ₂ is used. Thus, a thermal oxide film sidewall 8 composed of a thermal oxide film is formed on the side surfaces of the nitride film 3, the pad oxide film 2, and the first groove 4. The feature of this embodiment is that the thermal oxide film sidewall 8 is left without being removed until the element isolation formation is completed, thereby preventing the oxide film on the upper end portion of the trench, ie, generation of a divot. . Therefore, it is possible to prevent the electric field concentration at the upper end portion of the trench and suppress the reverse narrow channel effect. At this time, the opening diameter of the thermal oxide film sidewall 8 is 0.1 mm larger than the opening diameter of the nitride film 3.
The size is reduced by about 02 to 0.1 μm (FIG. 1
(E)).

Next, using the nitride film 3 and the thermal oxide film sidewall 8 as a mask, the second groove 9 having a depth of, for example, 200 nm is etched. At this time, H is used as an etching gas.
Using only the B _r, it is formed vertical grooves, or HB
A groove having a second taper angle may be formed by using a mixed gas of _r and O ₂ (FIG. 1F).

Next, thermal oxidation is performed in a dry atmosphere at 900 ° C. to form a thermal oxide film 10 on the bottom and side surfaces of the second groove. This thermal oxide film 10 functions as a layer for removing etching damage when the second groove 9 is etched. It is preferable that the thermal oxide film 10 has such a thickness that the groove 9 is not completely buried by the oxidation, or a hole (void) does not occur when the insulator is buried in the groove 9. , 5 to 50 nm (FIG. 1)
(G)).

Next, a CVD oxide film 11 as an element isolation insulating film is deposited on the entire surface of, for example, a 600 nm wafer to form a first
Groove 4 and second groove 9 are buried without excess or deficiency. The CVD oxide film used here is, for example, LPCVD, SACV
D, or NSG, B formed by APCVD
It may be PSG, BSG, PSG, or bias E
The same effect can be obtained with a plasma oxide film formed by a CRCVD method or the like (FIG. 1H).

Thereafter, until the upper surface of the nitride film 3 is exposed, CMP of the oxide film or etch back by anisotropic etching using CF ₄ as an etching gas is performed to planarize the buried oxide film (FIG. 1 (i) )).

Next, the nitride film 3 is formed using isotropic etching.
Then, the pad oxide film 2 is completely removed to obtain the structure shown in FIG. For example, wet etching is used for the isotropic etching, hot phosphoric acid is used for removing the nitride film,
Buffered hydrofluoric acid is used to remove the pad oxide film.
At this point, the thermal oxide film sidewall 8 formed in FIG. 1E remains at the upper end of the trench. Therefore, in the pad oxide film wet etching, the oxide film at the upper end of the trench does not retreat much (FIG. 1 (j)).

After that, a sacrificial oxide film is formed by thermally oxidizing the Si substrate (not shown), and various ions are implanted for adjusting the threshold value of the MOS transistor. The thermal oxide film is removed by using hydrofluoric acid to complete the formation of the trench isolation. Also in this case, since the thermal oxide film sidewall 8 is left at the upper end of the trench, the oxide film does not largely recede by wet etching, and the Si substrate at the upper end of the trench is not exposed to the surface. Subsequently, gate oxidation is performed in a dry atmosphere at 850 ° C. to form a gate oxide film 12, and then LPC is performed.
A gate polysilicon 13 is sequentially deposited by a VD method, and a tungsten silicide 14 is sequentially deposited by a sputtering method.
The structure shown in (k) is obtained.

FIG. 2 is an enlarged sectional view of the upper portion of the trench isolation, in which the dotted line portion in FIG. 1 (k) is enlarged. According to this method, the thermal oxide film sidewall 8 is left at the upper end portion of the trench isolation until the formation of the trench isolation is completed, so that the amount of retreat is minimized even after the oxide film wet etching that enters after the nitride film 3 is removed. Thus, the upper end of the trench can be prevented from being exposed. For this reason, it becomes possible to suppress the electric field concentration when a voltage is applied to the gate electrode.
Suppression of the inverse narrow channel effect of the S transistor can be realized.

In this method, the trench is etched in two stages using the thermal oxide film side wall 8. For this reason, it becomes possible to give a curvature to the shape of the upper end of the trench by giving a taper angle to the upper end of the trench,
The electric field concentration can be further alleviated. Further, according to the present invention, when the trench is completely buried with the CVD oxide film 11, the Si substrate 1 is protected by the thick thermal oxide film sidewall 8. For this reason, the ECRCVD
When the oxide film is used, the substrate is hardly damaged, and therefore, the deterioration of the junction leak can be prevented. Further, in this embodiment, since the trench upper end is protected by the thermal oxide film and the trench is tapered, it is not necessary to round the trench upper end using high-temperature oxidation. Accordingly, it is possible to prevent defocusing in lithography due to the warpage of the wafer, deterioration in alignment accuracy, and deterioration in junction leak characteristics due to occurrence of slip dislocation.

The above embodiment has been made to suppress the inverse narrow channel effect in a transistor using trench isolation for element isolation. For this purpose, in order to improve the shape of the trench upper end, a sidewall made of a thermal oxide film formed by utilizing thermal oxidation of polysilicon is formed at the trench upper end, and the thermal oxide film sidewall is removed. And remain until the trench isolation formation is completed. That is, a thermal oxide film formed by thermal oxidation is left at the upper end of the trench having the two-stage taper angle until the trench isolation formation is completed.

The thermal oxide film at the upper end of the trench is
It is formed by thermal oxidation of the polysilicon sidewall. That is, a groove having a two-stage taper angle is formed on the semiconductor substrate, and the thermal oxide film 10 is formed on the side and bottom surfaces thereof. The groove is completely buried by the thermal oxide film side wall 8 and the CVD oxide film 11, and the gate oxide film 12 and the gate polysilicon cover the groove. Here, the upper end of the trench (the dotted line in FIG. 2) is protected from the gate polysilicon 13 by the thermal oxide film sidewall 8 so that the electric field from the gate electrode is not concentrated.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0044]

As apparent from the above description, according to the semiconductor device and the method of manufacturing the semiconductor device of the present invention, the thermal oxide film formed by thermal oxidation is left until the trench isolation formation is completed. Therefore, the amount of recession of the oxide film at the upper end of the trench due to wet etching of the oxide film can be minimized. Further, the taper angle of the trench can be provided in two stages. For this reason, the upper end of the trench can have a curvature. As a result, the upper end of the trench having the curvature is not exposed. Therefore, it is possible to suppress electric field concentration when a voltage is applied to the gate electrode,
As a result, the inverse narrow channel effect of the MOS transistor can be suppressed.

According to the present invention, when the trench is completely buried with the CVD oxide film, the Si substrate is protected by the thick thermal oxide film sidewall. For this reason, when the ECRCVD oxide film is used as the burying material, the substrate is hardly damaged, and therefore, the deterioration of the junction leak can be prevented. In the present embodiment, the upper end of the trench is protected by the thermal oxide film, and the trench is tapered. This eliminates the need for rounding the upper end of the trench using high-temperature oxidation. Therefore, it is possible to prevent the defocus and alignment accuracy in lithography from deteriorating due to the warpage of the wafer and the junction leak characteristic from deteriorating due to the occurrence of slip dislocation.

[Brief description of the drawings]

FIG. 1 is a process chart showing an embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a sectional view showing an embodiment of the semiconductor device of the present invention.

FIG. 3 shows a conventional NM using trench isolation for element isolation.
FIG. 4 is a characteristic diagram showing a relationship between a threshold value Vt of an OS transistor and a channel width W.

FIG. 4 is a diagram for explaining a conventional semiconductor device;
(A) is a cross-sectional view of the trench isolation after the formation of the gate polycide electrode, and (b) is an enlarged view of a dotted line part in the figure.

FIG. 5 is a process chart showing a conventional semiconductor device manufacturing method 1;

FIG. 6 is a process chart showing a conventional method 2 of manufacturing a semiconductor device.

FIG. 7 is a process chart showing a conventional semiconductor device manufacturing method 3;

FIG. 8 is a cross-sectional configuration diagram showing a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (silicon substrate) 2 first insulating layer (pad oxide film) 3 second insulating layer (nitride film) 4 first groove 5 third insulating film (thermal oxide film) 6 polysilicon 7 Thermal oxide film 8 Thermal oxide film sidewall 9 Second groove 10 Thermal oxide film 11 CVD oxide film 12 Gate oxide film 13 Gate polysilicon 14 Tungsten silicide

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/76 H01L 21/76 L 21/3205 21/88 B F-term (Reference) 4M104 AA01 BB01 CC05 DD37 DD43 FF14 GG09 HH18 5F032 AA16 AA36 AA44 AA49 AA67 AA70 AA77 CA17 DA02 DA03 DA25 DA28 DA30 DA33 DA53 5F033 AA02 AA04 AA17 AA54 AA63 AA65 AA66 AA75 BA02 BA15 BA33 BA37 CA04 5F040 DA00 DC01 EC01 EC01 EC01 EC01 EC01 EC01 EC01 EC01 EC01 EC01 BF03 BF04 BF09 BF62 BH20 BJ06

Claims (8)

[Claims] 1. A groove (trench) having a two-stage taper angle formed on a semiconductor substrate, a thermal oxide film formed on side and bottom surfaces of the groove, and a thermal oxide film sidewall burying the groove. And CVD
An oxide film, a gate oxide film, a gate oxide film, a gate polysilicon film covering the thermal oxide film sidewall and a CVD oxide film, and an upper end of the trench is formed by the thermal oxide film sidewall. A semiconductor device protected from the gate polysilicon. 2. The semiconductor device according to claim 1, wherein said two-stage taper angle is formed in said groove to avoid concentration of electric charges on a corner of said groove. 3. The semiconductor device according to claim 1, wherein the semiconductor device is configured by further covering the gate polysilicon with silicide or metal. 4. The semiconductor device according to claim 1, wherein said semiconductor substrate is a silicon substrate. 5. A step of forming a pad oxide film by oxidizing a surface of a semiconductor substrate; a step of depositing a film functioning as a stopper when the buried oxide film is planarized on the pad oxide film; Providing an opening by processing by dry etching; forming a first groove (trench) having a taper; forming a thermal oxide film by thermal oxidation on side and bottom surfaces of the first groove; Depositing polysilicon over the entire surface of the wafer by an LPCVD method, forming a thermal oxide film by thermally oxidizing the polysilicon, etching back the thermal oxide film by anisotropic etching to form the semiconductor substrate and Exposing a stopper layer and forming an oxide film sidewall formed by the thermal oxidation at an upper end of the trench; Vertically forming a second groove using the stopper layer and the thermal oxide film sidewall as a mask; thermally oxidizing side and bottom surfaces of the second groove to form a thermal oxide film; Embedding the groove and the second groove with a CVD oxide film, removing the CVD oxide film deposited on the stopper layer until the stopper layer is exposed, and slightly etching the thermal oxide film sidewalls A step of removing the stopper layer and the pad oxide film by isotropic etching such as wet etching, and a step of performing ion implantation for threshold value adjustment through a sacrificial oxide film formed by the thermal oxidation. A method for manufacturing a semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising:
6. The method according to claim 5, further comprising a step of sequentially depositing a gate oxide film, a gate polysilicon, a silicide, or a metal after the ion implantation. 7. The method according to claim 5, wherein the film functioning as a stopper when the buried oxide film is planarized is a nitride film. 8. The method according to claim 5, wherein the removal of the CVD oxide film is performed by CMP or dry etching.
8. The method for manufacturing a semiconductor device according to any one of items 1 to 7.