JP3439387B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3439387B2 JP3439387B2 JP21234199A JP21234199A JP3439387B2 JP 3439387 B2 JP3439387 B2 JP 3439387B2 JP 21234199 A JP21234199 A JP 21234199A JP 21234199 A JP21234199 A JP 21234199A JP 3439387 B2 JP3439387 B2 JP 3439387B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- etching
- semiconductor device
- semiconductor substrate
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にトレンチ素子分離領域の形成方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a trench element isolation region.
【０００２】[0002]
【従来の技術】半導体素子の微細化や高速化を図る上
で、素子分離の間隔を狭めることが必要になっている。
従来、素子分離領域を形成する方法としては、ＬＯＣＯ
Ｓ法が一般的であったが、このような微細化の要求には
十分対応できない。そこで、このＬＯＣＯＳ法に代わる
方法として、最近、ＳＴＩ（Shallow Trench Isolatio
n）が注目されている。2. Description of the Related Art In order to miniaturize and speed up a semiconductor device, it is necessary to narrow an element separation interval.
Conventionally, LOCO has been used as a method for forming the element isolation region.
Although the S method is generally used, it cannot sufficiently meet such a demand for miniaturization. Therefore, as an alternative method to the LOCOS method, recently, STI (Shallow Trench Isolation)
n) is receiving attention.
【０００３】従来のＳＴＩでは、シリコン基板などの半
導体基板上に薄いパッド酸化膜、窒化膜を積層し、フォ
トリソグラフィー法により素子分離する領域を開口した
レジストマスクを形成し、これをマスクに窒化膜、パッ
ド酸化膜、半導体基板を異方性エッチングして、溝（ト
レンチ）を形成し、レジストマスクを除去した後、絶縁
性物質を全面に堆積し、窒化膜をストッパとして化学機
械研磨（Chemical Mechanical Polishing: ＣＭＰ）に
より、前記トレンチに絶縁物質を埋め込んで素子分離を
形成していた。In the conventional STI, a thin pad oxide film and a nitride film are laminated on a semiconductor substrate such as a silicon substrate, and a resist mask having an opening for element isolation is formed by a photolithography method. Anisotropically etch the pad oxide film and the semiconductor substrate to form a groove (trench), remove the resist mask, deposit an insulating material on the entire surface, and use the nitride film as a stopper to perform chemical mechanical polishing (Chemical Mechanical Polishing). The trenches are filled with an insulating material by Polishing: CMP) to form element isolations.
【０００４】トレンチ内に絶縁物を埋め込む際に、トレ
ンチ形成の際のエッチングダメージを解消する目的でト
レンチ内壁を熱酸化することが一般的に行われている。[0006] When an insulator is embedded in the trench, the inner wall of the trench is generally thermally oxidized for the purpose of eliminating etching damage when the trench is formed.
【０００５】このようなトレンチ素子分離を用いた半導
体装置では、トレンチ素子分離領域に接してトランジス
タなどが形成されるが、この時、トレンチ縁部の形状が
鋭角であると、その部分で電界集中を起こし、トランジ
スタの閾値特性が悪化するするという問題がある。つま
り、図５（ａ）に示すように、トレンチ素子分離で区画
された素子領域５２において、ゲート電極５１はトレン
チ素子分離領域にも架かって形成されるが、そのとき、
トレンチ縁部に隣接してサブチャネル５３が形成され、
メインのチャネルとサブチャネルとのゲート電圧に対す
るドレイン電流特性が異なることから、図５（ｂ）に示
すように通常の閾値電圧を有するメインのチャネルと活
性領域の縁部に寄生する相対的に低い閾値電圧を有する
サブチャネルによって前記トランジスタは、動作中に閾
値電圧が変化するようになり、サブチャネルによる閾値
領域で電流のハンプ現象を起こす。従って、トランジス
タのリーク電流の増加およびオン・オフ特性の劣化を招
く。このような問題点は、素子のチャネル幅が狭くなる
ほど、即ち、集積度が高くなるほど顕著になる。In a semiconductor device using such trench element isolation, a transistor or the like is formed in contact with the trench element isolation region. At this time, if the shape of the trench edge is an acute angle, the electric field is concentrated at that portion. And the threshold characteristic of the transistor is deteriorated. That is, as shown in FIG. 5A, in the element region 52 partitioned by the trench element isolation, the gate electrode 51 is formed so as to extend over the trench element isolation region as well.
Subchannel 53 is formed adjacent to the edge of the trench,
Since the drain current characteristics with respect to the gate voltage of the main channel and the sub-channel are different from each other, as shown in FIG. 5B, the main channel having a normal threshold voltage and the relatively low parasitic parasitic on the edge of the active region are included. The sub-channel having the threshold voltage causes the threshold voltage of the transistor to change during operation, causing a current hump phenomenon in the threshold region of the sub-channel. Therefore, an increase in leak current of the transistor and deterioration of on / off characteristics are caused. Such a problem becomes more remarkable as the channel width of the device becomes narrower, that is, as the degree of integration increases.
【０００６】そこで、従来、このようなＳＴＩにおける
ハンプの発生を防止するため、トレンチ縁部を丸める方
法が提案されている。通常、トレンチ縁部を丸めるに
は、上記のトレンチ内部の熱酸化を高温で行う方法が採
られていた。Therefore, conventionally, a method of rounding the trench edge has been proposed in order to prevent the occurrence of hump in such STI. Usually, in order to round the trench edge, a method of performing the thermal oxidation inside the trench at a high temperature has been adopted.
【０００７】しかしながら、図３に示すように、半導体
基板として通常使用されている（１１１）シリコン基板
３１を用いた場合、高温（１１００℃程度）での熱酸化
ではトレンチ底の角部に＜１１１＞面の結晶面３３（フ
ァセット）が出現し、熱酸化膜の応力によって転位が発
生してしまう。これが転位ループ３２として後工程で形
成されるトランジスタのソース・ドレイン領域まで達
し、電気特性が悪化するという問題がある。However, as shown in FIG. 3, when a (111) silicon substrate 31 which is usually used as a semiconductor substrate is used, thermal oxidation at a high temperature (about 1100 ° C.) results in <111 at the corner of the trench bottom. The crystal plane 33 (facet) of the> plane appears, and dislocation occurs due to the stress of the thermal oxide film. This reaches the source / drain regions of the transistor that will be formed as a dislocation loop 32 in a later step, and there is a problem that the electrical characteristics deteriorate.
【０００８】一方、ウェット酸化はドライ酸化と比較し
て酸化膜成長速度が速く、所望の膜厚の熱酸化膜を得る
に際しては、酸化時間が同じであれば、より低温での熱
酸化が可能である。低温のウェット酸化ではファセット
は発生しにくくなるが、図４に示すように、膜厚の均一
性がドライ酸化と比較してやや劣っており、またトレン
チ縁部４１を十分に丸めることができず、上記のハンプ
発生を防止することができない。On the other hand, wet oxidation has a higher oxide film growth rate than dry oxidation, and when a thermal oxide film having a desired film thickness is obtained, thermal oxidation at a lower temperature is possible if the oxidation time is the same. Is. Facet is less likely to occur in the low temperature wet oxidation, but as shown in FIG. 4, the film thickness uniformity is slightly inferior to that in the dry oxidation, and the trench edge portion 41 cannot be sufficiently rounded. The above hump cannot be prevented.
【０００９】ところで、特開平１１−１３５６０８号公
報、同１１−１３５６０９号公報、同１１−１３５６１
０号公報には、トレンチ形成時の異方性エッチングによ
るシリコン基板へのダメージを素子形成領域から遠ざけ
るために、開口に露出した半導体基板を等方的にエッチ
ングして、異方性エッチングのハードマスクとなるシリ
コン酸化膜を庇状に張り出させ、これを用いて異方性エ
ッチングしてトレンチを形成する方法が提案されてい
る。例えば、特開平１１−１３５６０８号公報を例に説
明すると、まず、図６（ａ）に示すように、Ｓｉ基板１
などの半導体基板上に薄いパッド酸化膜２を熱酸化法な
どにより形成し、続いて、シリコン窒化膜３をＬＰＣＶ
Ｄ法などにより所望の厚みに形成する。更にその上にシ
リコン酸化膜４をＬＰＣＶＤ法などにより１０００〜２
０００Å程度の厚みに形成する。続いて、レジストを塗
布し、通常のフォトリソ工程により素子分離を形成する
部分を開口するようにレジストマスク５を形成し、これ
をマスクに酸化膜４をドライエッチングする。レジスト
マスクを除去した後、パターン化された酸化膜４をマス
クに窒化膜３、パッド酸化膜を順次ドライエッチング
し、更に、露出したシリコン基板表面を浅く（３００〜
１０００Å）ドライエッチングして開口６’を形成する
（図６（ｂ））。続いて露出したＳｉ基板１表面を熱酸
化し、１００〜２００Åの熱酸化膜１１を形成し（図６
（ｃ））、該熱酸化膜１１を除去して、浅い溝７’を形
成すると共に、シリコン窒化膜及びシリコン酸化膜を庇
状に張り出させておく（図６（ｄ））。前記酸化膜４を
マスクに露出したＳｉ基板１表面をドライエッチングし
て２０００〜４０００Å程度のトレンチ８を形成する
（図７（ａ））。この後、トレンチ内部を９００℃以上
のドライ酸化或いは８００℃以上のウェット酸化により
熱酸化して、１００〜２００Åの熱酸化膜９を形成し
（図７（ｂ））、ＣＶＤ法により全面に厚いＣＶＤ酸化
膜１０を堆積し（図７（ｃ））、窒化膜３をストッパと
して化学機械研磨（ＣＭＰ）法にてＣＶＤ酸化膜１０を
研磨する（図７（ｄ））ことでトレンチ素子分離を形成
する方法である。By the way, JP-A-11-135608, JP-A-11-135609, and JP-A-11-13561.
In Japanese Unexamined Patent Application Publication No. 0-331, in order to prevent damage to the silicon substrate due to anisotropic etching at the time of forming a trench away from the element formation region, the semiconductor substrate exposed in the opening is isotropically etched and an anisotropic etching hard mask is used. A method has been proposed in which a silicon oxide film serving as a mask is projected in an eaves-like shape, and anisotropic etching is performed using this to form a trench. For example, taking Japanese Patent Laid-Open No. 11-135608 as an example, first, as shown in FIG.
A thin pad oxide film 2 is formed on a semiconductor substrate such as by a thermal oxidation method, and then a silicon nitride film 3 is formed by LPCV.
The desired thickness is formed by the D method or the like. Further, a silicon oxide film 4 is formed on the insulating film by the LPCVD method or the like by 1000-2.
Form to a thickness of about 000Å. Subsequently, a resist is applied, and a resist mask 5 is formed by an ordinary photolithography process so as to open a portion where element isolation is to be formed, and the oxide film 4 is dry-etched using this as a mask. After removing the resist mask, the nitride film 3 and the pad oxide film are sequentially dry-etched using the patterned oxide film 4 as a mask, and the exposed silicon substrate surface is shallowed (300-
1000Å) Dry etching is performed to form an opening 6 '(FIG. 6 (b)). Then, the exposed surface of the Si substrate 1 is thermally oxidized to form a thermal oxide film 11 of 100 to 200 Å (see FIG. 6).
(C)) The thermal oxide film 11 is removed to form the shallow groove 7'and the silicon nitride film and the silicon oxide film are overhanged in an eaves-like shape (FIG. 6 (d)). The surface of the Si substrate 1 exposed with the oxide film 4 as a mask is dry-etched to form a trench 8 of about 2000 to 4000 Å (FIG. 7A). After that, the inside of the trench is thermally oxidized by dry oxidation at 900 ° C. or higher or wet oxidation at 800 ° C. or higher to form a thermal oxide film 9 of 100 to 200 Å (FIG. 7 (b)), and the entire surface is thickened by the CVD method. The CVD oxide film 10 is deposited (FIG. 7C), and the CVD oxide film 10 is polished by the chemical mechanical polishing (CMP) method using the nitride film 3 as a stopper (FIG. 7D) to isolate trench elements. It is a method of forming.
【００１０】しかしながら、これらの従来技術では、前
記のハンプや、ファセットの問題について言及されてい
ない。However, in these prior arts, the above-mentioned problem of hump and facet is not mentioned.
【００１１】[0011]
【発明が解決しようとする課題】本発明の目的は、高温
のドライ酸化にみられるような上記ファセットによる転
位ループの発生を抑制して電気特性の悪化を防止すると
共に、従来のウェット酸化ではトレンチ縁部の形状が十
分丸くできないことに起因するＳＴＩのハンプによるト
ランジスタのリーク電流の増加およびオン・オフ特性の
劣化を防止することのできるトレンチ形成工程を有する
半導体装置の製造方法を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to suppress the occurrence of dislocation loops due to the above facets as seen in high temperature dry oxidation to prevent the deterioration of electrical characteristics, and to reduce trenches in conventional wet oxidation. Provided is a method of manufacturing a semiconductor device having a trench forming step capable of preventing an increase in leak current and deterioration of on / off characteristics of a transistor due to STI hump due to an insufficiently rounded edge shape. is there.
【００１２】[0012]
【課題を解決するための手段】本発明者は、上記課題を
解決するべく鋭意検討した結果、トレンチ縁部に当たる
部分を予め等方性エッチングで除去しておき、その後異
方性エッチングでトレンチを形成しておくことで、その
後の低温でのウェット熱酸化によってもトレンチ縁部を
丸くすることができ、低温熱酸化であるためにファセッ
トの発生を防止できることを見出した。Means for Solving the Problems As a result of intensive studies to solve the above-mentioned problems, the present inventor has previously removed a portion corresponding to the edge of the trench by isotropic etching and then anisotropically etching the trench. It has been found that by forming it, the edge of the trench can be rounded even by subsequent wet thermal oxidation at low temperature, and facet generation can be prevented because of low temperature thermal oxidation.
【００１３】すなわち、本発明は、半導体基板上に、パ
ッド酸化膜、シリコン窒化膜を順次成膜する工程、シリ
コン窒化膜上にレジストを塗布し、トレンチ形成のため
のパターンを形成する工程、形成されたレジストパター
ンをマスクとして、シリコン窒化膜、パッド酸化膜を順
次エッチングして、開口を形成する工程、該開口部内に
露出したパッド酸化膜をウェットエッチングによりサイ
ドエッチングし、更に開口部底に露出した半導体基板表
面を等方性エッチングして半導体基板表面に浅い溝を形
成する工程、シリコン基板を異方性エッチングして、深
い溝を形成する工程、該溝内に低温のウエット酸化によ
り熱酸化膜を形成する工程、前記溝を埋めるように全面
に絶縁物を堆積する工程、前記シリコン窒化膜をストッ
パとして絶縁物をＣＭＰ研磨して平坦化する工程とを有
することを特徴とする半導体装置の製造方法である。That is, according to the present invention, a step of sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate, a step of applying a resist on the silicon nitride film to form a pattern for forming a trench, and a formation Using the formed resist pattern as a mask, the silicon nitride film and the pad oxide film are sequentially etched to form an opening, the pad oxide film exposed in the opening is side-etched by wet etching, and further exposed to the bottom of the opening. Isotropically etching the surface of the semiconductor substrate to form a shallow groove on the surface of the semiconductor substrate, anisotropically etching the silicon substrate to form a deep groove, and thermally oxidizing the groove by low temperature wet oxidation. A step of forming a film, a step of depositing an insulator on the entire surface so as to fill the groove, and an insulator using the silicon nitride film as a stopper. A method of manufacturing a semiconductor device characterized by a step of flattening by MP polished.
【００１４】[0014]
【発明の実施の形態】本発明においては、トレンチ形成
時に絶縁物ハードマスク開口面に露出する最下層のパッ
ド酸化膜にサイドエッチングを施し、これをマスクにシ
リコン基板を等方性エッチングして浅い溝を形成してい
るため、パッド酸化膜のサイドエッチング量を調整する
ことにより、容易にシリコン基板の等方性エッチングに
よるハードマスク下への入り込み量を調整することがで
きる。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, side etching is performed on a lowermost pad oxide film exposed on an opening surface of an insulator hard mask at the time of forming a trench, and a silicon substrate is isotropically etched by using this as a mask to make a shallow etch. Since the groove is formed, by adjusting the side etching amount of the pad oxide film, it is possible to easily adjust the entering amount of the silicon substrate under the hard mask due to isotropic etching.
【００１５】ここで、パッド酸化膜に施すサイドエッチ
ングの開口端面からの距離（サイドエッチング量）は、
あまり少なすぎると、シリコン基板の等方性エッチング
によって形成する浅い溝のハードマスク下への入り込み
量が少なくなってしまう。もちろん、等方性エッチング
によるエッチング量を多くすれば入り込み量を確保する
ことができるが、その分溝深さが深くなってしまう。サ
イドエッチング量としては、５０〜３００Å、より好ま
しくは５０〜２００Åである。Here, the distance (side etching amount) from the opening end face of the side etching applied to the pad oxide film is
If the amount is too small, the amount of shallow grooves formed by isotropic etching of the silicon substrate under the hard mask will be small. Of course, if the amount of etching by isotropic etching is increased, the amount of penetration can be secured, but the groove depth will be correspondingly increased. The side etching amount is 50 to 300Å, more preferably 50 to 200Å.
【００１６】本発明においてハードマスク形成時の異方
性エッチングでは、パッド酸化膜を完全に除去してシリ
コン基板を露出させても良いが、完全に除去せずにシリ
コン基板表面に薄いパッド酸化膜が残った状態のままで
あっても、パッド酸化膜のサイドエッチングの際のウェ
ットエッチングで除去することができる。In the present invention, in the anisotropic etching for forming the hard mask, the pad oxide film may be completely removed to expose the silicon substrate, but the thin pad oxide film is not completely removed on the surface of the silicon substrate. Even in the state in which the oxide is left, it can be removed by wet etching during side etching of the pad oxide film.
【００１７】続いて、シリコン基板の等方性エッチング
により浅い溝を形成するが、その際の等方性エッチング
は、プラズマエッチング等のドライエッチング、アンモ
ニア及び過酸化水素を用いたウェットエッチングのいず
れの方法でも良い。又、溝の深さとしては１００〜５０
０Å、より好ましくは１００〜３００Åである。Subsequently, a shallow groove is formed by isotropic etching of the silicon substrate. At this time, the isotropic etching is either dry etching such as plasma etching or wet etching using ammonia and hydrogen peroxide. The method is also good. The depth of the groove is 100-50.
It is 0Å, more preferably 100 to 300Å.
【００１８】シリコン基板へのトレンチ形成のための異
方性エッチングは、ハードマスク形成時のレジストマス
クをマスクとして行っても、レジストマスクを除去して
窒化膜をマスクとして行っても良いが、好ましくは、窒
化膜上に更にシリコン酸化膜を形成しておき、レジスト
除去後にこのシリコン酸化膜をマスクにシリコン基板へ
の異方性エッチングを行うのが望ましい。尚、異方性エ
ッチング時のマスクとしてレジストマスクを使用する場
合、その前に実施する等方性エッチングは、ウェットエ
ッチングではレジストマスクが剥離してしまうため、ド
ライエッチングで行う。The anisotropic etching for forming the trench in the silicon substrate may be performed by using the resist mask at the time of forming the hard mask as a mask or by removing the resist mask and using the nitride film as a mask, but it is preferable. It is preferable that a silicon oxide film is further formed on the nitride film, and after the resist is removed, anisotropic etching is performed on the silicon substrate using the silicon oxide film as a mask. When a resist mask is used as a mask for anisotropic etching, isotropic etching performed before that is dry etching because the resist mask is peeled off by wet etching.
【００１９】このようにして、トレンチを形成した後、
トレンチ内に露出したシリコン基板表面に低温のウエッ
ト酸化により熱酸化膜を形成する。ウェット酸化法とし
ては従来公知のウェットＯ2酸化やスチーム酸化を採用
することができる。ウェット酸化温度としては、８００
〜１０００℃、より好ましくは８００〜９００℃の温度
範囲で行うのが望ましい。ここでは、熱酸化膜として１
００〜５００Å程度の膜厚に形成する。例えば、スチー
ム酸化では９００℃で５分程度、８００℃では１０〜２
０分程度行えばよい。After forming the trench in this way,
A thermal oxide film is formed on the surface of the silicon substrate exposed in the trench by low temperature wet oxidation. As the wet oxidation method, conventionally known wet O 2 oxidation or steam oxidation can be adopted. Wet oxidation temperature is 800
It is desirable to carry out in the temperature range of ˜1000 ° C., more preferably 800˜900 ° C. Here, the thermal oxide film is 1
The film is formed to a film thickness of about 00 to 500Å. For example, steam oxidation takes about 5 minutes at 900 ° C and 10-2 at 800 ° C.
It only has to be done for about 0 minutes.
【００２０】続いて、従来法と同様にトレンチ内にＣＶ
Ｄ酸化膜などの絶縁物を埋め込み、窒化膜をストッパと
してＣＭＰ研磨して、絶縁物をトレンチ内に埋め込む。Then, the CV is formed in the trench as in the conventional method.
An insulator such as a D oxide film is embedded, and CMP polishing is performed using the nitride film as a stopper to fill the trench with the insulator.
【００２１】本発明では、シリコン基板に等方性エッチ
ングにより浅い溝を形成しているので、低温のウェット
酸化によってもトレンチ縁部を丸くすることができ、し
かもトレンチ底ではファセットの発生が防止できるの
で、転位ループが発生することもない。In the present invention, since the shallow groove is formed in the silicon substrate by isotropic etching, the trench edge can be rounded even by low temperature wet oxidation, and facet formation at the trench bottom can be prevented. Therefore, the dislocation loop does not occur.
【００２２】[0022]
【実施例】以下、実施例により本発明を具体的に説明す
るが、本発明はこれらの実施例のみに限定されるもので
はない。EXAMPLES The present invention will be specifically described below with reference to examples, but the present invention is not limited to these examples.
【００２３】実施例１
図面を参照して本発明の第１の実施例を説明する。図
１、２は、本発明の第１の実施例に係る半導体装置の製
造方法の工程断面図である。First Embodiment A first embodiment of the present invention will be described with reference to the drawings. 1 and 2 are process cross-sectional views of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
【００２４】まず、Ｓｉ基板１を９００℃、Ｈ2−Ｏ2雰
囲気中で熱酸化して、２００Å程度の厚みのパッド酸化
膜２を形成し、その上に、シラン及びアンモニアを原料
ガスとして、７００〜８００℃程度の温度範囲でＬＰＣ
ＶＤ法により窒化膜（Ｓｉ3Ｎ4）膜３を１５００Å程度
の厚みに成膜する。更に、ＴＥＯＳを原料として６５０
〜７００℃の温度範囲でＬＰＣＶＤ法により５００Å程
度の膜厚のＣＶＤシリコン酸化膜（ＳｉＯ2）膜４を形
成する（図１（ａ））。First, the Si substrate 1 is thermally oxidized in a H 2 —O 2 atmosphere at 900 ° C. to form a pad oxide film 2 having a thickness of about 200 Å, and silane and ammonia are used as source gases on the pad oxide film 2. LPC in the temperature range of 700-800 ℃
A nitride film (Si 3 N 4 ) film 3 is formed to a thickness of about 1500 Å by the VD method. Furthermore, using TEOS as a raw material, 650
A CVD silicon oxide film (SiO 2 ) film 4 having a film thickness of about 500 Å is formed by LPCVD in the temperature range of up to 700 ° C. (FIG. 1A).
【００２５】続いて、酸化膜４上にレジストを塗布し、
フォトリソ工程により所定のパターンを形成してレジス
トマスク５とし、このレジストマスク５をマスクとして
酸化膜４、窒化膜３、パッド酸化膜２をそれぞれ異方性
ドライエッチングし、開口６を形成する（図１
（ｂ））。Subsequently, a resist is applied on the oxide film 4,
A predetermined pattern is formed by a photolithography process to form a resist mask 5, and the oxide film 4, the nitride film 3, and the pad oxide film 2 are anisotropically dry-etched using the resist mask 5 as a mask to form an opening 6 (FIG. 1
(B)).
【００２６】Ｏ2プラズマによりアッシングし、レジス
ト剥離液を用いてレジストマスク５及び開口６内壁に付
着したエッチング残渣を除去した後、フッ酸系エッチン
グ液を用いてパッド酸化膜２に、１００Å程度のサイド
エッチングを施す。続いて、アンモニア及び過酸化水素
を用いたエッチング液により、開口内に露出しているシ
リコン基板１表面に浅い溝７を等方性エッチングにより
形成する（図１（ｃ））。ここでは、溝深さとして２０
０Å程度の深さとする。続いて酸化膜４をマスクとして
浅い溝７底に露出したＳｉ基板１をドライエッチング
し、トレンチ８を形成する（図１（ｄ））。ここでは、
トレンチ深さとして、２５００Åのトレンチを形成し
た。After ashing with O 2 plasma and removing the etching residue adhering to the resist mask 5 and the inner wall of the opening 6 with a resist stripping solution, the pad oxide film 2 with a hydrofluoric acid-based etching solution of about 100 liters is removed. Perform side etching. Then, a shallow groove 7 is formed by isotropic etching on the surface of the silicon substrate 1 exposed in the opening with an etching solution using ammonia and hydrogen peroxide (FIG. 1C). Here, the groove depth is 20
The depth should be about 0Å. Then, using the oxide film 4 as a mask, the Si substrate 1 exposed at the bottom of the shallow groove 7 is dry-etched to form a trench 8 (FIG. 1D). here,
As a trench depth, a 2500 Å trench was formed.
【００２７】続いて、Ｏ2雰囲気下、９００℃でウェッ
ト熱酸化して、トレンチ内壁に４００Å程度の熱酸化膜
９を形成した（図２（ａ））。Subsequently, wet thermal oxidation was performed at 900 ° C. in an O 2 atmosphere to form a thermal oxide film 9 of about 400 Å on the inner wall of the trench (FIG. 2A).
【００２８】このように形成したトレンチ内部に酸化膜
を埋め込むため、まず、図２（ｂ）に示すように全面に
ＨＤＰＣＶＤ法により５５００Å程度の厚みにＣＶＤ酸
化膜１０を成膜した。続いて、窒化膜３をＣＭＰストッ
パとして、ＣＶＤ酸化膜１０及び酸化膜４をＣＭＰ法に
より研磨し、図２（ｃ）に示す構造を得た。更に窒化膜
３を熱リン酸で除去し、パッド酸化膜２をフッ酸系溶液
で除去することで、図２（ｄ）に示すようなトレンチ素
子分離が形成された。In order to bury the oxide film in the trench thus formed, first, as shown in FIG. 2B, the CVD oxide film 10 was formed on the entire surface by the HDPCVD method to a thickness of about 5500 Å. Then, using the nitride film 3 as a CMP stopper, the CVD oxide film 10 and the oxide film 4 were polished by the CMP method to obtain the structure shown in FIG. Further, the nitride film 3 was removed with hot phosphoric acid, and the pad oxide film 2 was removed with a hydrofluoric acid-based solution, so that trench element isolation as shown in FIG. 2D was formed.
【００２９】[0029]
【発明の効果】以上説明したように、本発明によれば、
パッド酸化膜をサイドエッチングし、更に、シリコン基
板を等方性エッチングして浅い溝を形成した後、異方性
エッチングでトレンチを形成し、このように形成された
トレンチ内をウェット酸化により熱酸化して熱酸化膜を
形成しているので、高温のドライ酸化にみられるような
ファセットによる転位ループの発生が抑えられ、電気特
性の悪化を防止することができると同時に、ウェット酸
化では従来十分丸めることができなかったトレンチ縁部
を丸めることができ、ＳＴＩのハンプによるトランジス
タのリーク電流の増加およびオン・オフ特性の劣化を防
止することができる。As described above, according to the present invention,
After the pad oxide film is side-etched and the silicon substrate is isotropically etched to form a shallow groove, a trench is formed by anisotropic etching, and the trench thus formed is thermally oxidized by wet oxidation. Since the thermal oxide film is formed by using it, generation of dislocation loops due to facets, which is observed in high temperature dry oxidation, can be suppressed, and deterioration of electrical characteristics can be prevented. It is possible to round the edge portion of the trench that could not be formed, and it is possible to prevent an increase in the leakage current of the transistor and deterioration of the on / off characteristics due to the hump of the STI.
【図１】本発明の第１の実施例になる半導体装置の製造
工程断面図である。FIG. 1 is a cross-sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.
【図２】本発明の第１の実施例になる半導体装置の製造
工程断面図である。FIG. 2 is a cross-sectional view of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.
【図３】ドライ酸化による問題点を説明する概念図であ
り、（ｂ）は、（ａ）の部分拡大図である。FIG. 3 is a conceptual diagram illustrating a problem caused by dry oxidation, and FIG. 3B is a partially enlarged view of FIG.
【図４】ウェット酸化による問題点を説明する概念図で
ある。FIG. 4 is a conceptual diagram illustrating a problem caused by wet oxidation.
【図５】（ａ）はトレンチ縁部の近傍にサブチャネルが
形成される様子を模式的に示す平面図であり、（ｂ）は
このようなサブチャネルの形成によるハンプの発生を説
明するグラフである。FIG. 5A is a plan view schematically showing how a sub-channel is formed in the vicinity of the edge of the trench, and FIG. 5B is a graph explaining the occurrence of hump due to the formation of such a sub-channel. Is.
【図６】従来技術になる半導体装置の製造工程断面図で
ある。FIG. 6 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.
【図７】従来技術になる半導体装置の製造工程断面図で
ある。FIG. 7 is a cross-sectional view of manufacturing steps of a conventional semiconductor device.
１ Ｓｉ基板 ２ パッド酸化膜 ３ 窒化膜 ４ 酸化膜 ５ レジストマスク ６ 開口 ７ 浅い溝 ８ トレンチ ９ 熱酸化膜 １０ ＣＶＤ酸化膜 1 Si substrate 2 Pad oxide film 3 Nitride film 4 oxide film 5 Resist mask 6 openings 7 shallow groove 8 trench 9 Thermal oxide film 10 CVD oxide film
フロントページの続き (56)参考文献 特開2000−340558（ＪＰ，Ａ) 特開 昭60−128634（ＪＰ，Ａ) 特開 昭58−9333（ＪＰ，Ａ) 特開 平11−135609（ＪＰ，Ａ) 特開 平11−8303（ＪＰ，Ａ) 特開 平１−107554（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/76 - 21/765 Continuation of the front page (56) Reference JP 2000-340558 (JP, A) JP 60-128634 (JP, A) JP 58-9333 (JP, A) JP 11-135609 (JP, A) JP-A-11-8303 (JP, A) JP-A-1-107554 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/76-21/765
Claims (7)
ン窒化膜を順次成膜する工程、シリコン窒化膜上にレジ
ストを塗布し、トレンチ形成のためのパターンを形成す
る工程、形成されたレジストパターンをマスクとして、
シリコン窒化膜、パッド酸化膜を順次エッチングして、
開口を形成する工程、該開口部内に露出したパッド酸化
膜をウエットエッチングにより５０〜３００Åの範囲で
サイドエッチングし、更に開口部底に露出した半導体基
板表面を等方性エッチングして半導体基板表面に浅い溝
を形成する工程、シリコン基板を異方性エッチングし
て、深い溝を形成する工程、前記工程に続いて該溝内に
８００℃以上１０００℃未満の温度条件でウエット酸化
により熱酸化膜を形成する工程、前記溝を埋めるように
全面に絶縁物を堆積する工程、前記シリコン窒化膜をス
トッパとして絶縁物をＣＭＰ研磨して平坦化する工程と
を有することを特徴とする半導体装置の製造方法。1. A step of sequentially forming a pad oxide film and a silicon nitride film on a semiconductor substrate, a step of applying a resist on the silicon nitride film to form a pattern for trench formation, and a formed resist pattern. As a mask
The silicon nitride film and the pad oxide film are sequentially etched,
In the step of forming an opening, the pad oxide film exposed in the opening is side-etched by wet etching in the range of 50 to 300Å, and the semiconductor substrate surface exposed at the bottom of the opening is isotropically etched to form a semiconductor substrate surface. A step of forming a shallow groove, a step of anisotropically etching a silicon substrate to form a deep groove, and subsequent to the above step, a thermal oxide film is formed in the groove by wet oxidation under a temperature condition of 800 ° C. or more and less than 1000 ° C. A method of manufacturing a semiconductor device, comprising: a step of forming, an step of depositing an insulator on the entire surface so as to fill the groove, and a step of planarizing the insulator by CMP polishing using the silicon nitride film as a stopper. .
ライ条件で行うことを特徴とする請求項１に記載の半導
体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching of the semiconductor substrate is performed under dry conditions.
ンモニア及び過酸化水素を用いたウエットエッチングに
て行うことを特徴とする請求項１に記載の半導体装置の
製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein the isotropic etching of the semiconductor substrate is performed by wet etching using ammonia and hydrogen peroxide.
ジストパターンをマスクに行うことを特徴とする請求項
２に記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 2, wherein anisotropic etching of the semiconductor substrate is performed using a resist pattern as a mask.
リコン窒化膜をマスクに行うことを特徴とする請求項１
に記載の半導体装置の製造方法。5. The anisotropic etching of the semiconductor substrate is performed using a silicon nitride film as a mask.
A method of manufacturing a semiconductor device according to item 1.
化膜を形成し、開口を形成した後、半導体基板の異方性
エッチングを該シリコン酸化膜をマスクに行うことを特
徴とする請求項２又は３に記載の半導体装置の製造方
法。6. A silicon oxide film is further formed on the silicon nitride film to form an opening, and then anisotropic etching of the semiconductor substrate is performed using the silicon oxide film as a mask. 4. The method for manufacturing a semiconductor device according to item 3.
フッ酸系溶液を用いて行うことを特徴とする請求項１に
記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 1, wherein side etching of the pad oxide film is performed using a hydrofluoric acid-based solution.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21234199A JP3439387B2 (en) | 1999-07-27 | 1999-07-27 | Method for manufacturing semiconductor device |
| KR10-2000-0042978A KR100381399B1 (en) | 1999-07-27 | 2000-07-26 | Manufacture of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21234199A JP3439387B2 (en) | 1999-07-27 | 1999-07-27 | Method for manufacturing semiconductor device |
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| Publication Number | Publication Date |
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| JP2001044273A JP2001044273A (en) | 2001-02-16 |
| JP3439387B2 true JP3439387B2 (en) | 2003-08-25 |
Family
ID=16620942
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|---|---|---|---|
| JP21234199A Expired - Fee Related JP3439387B2 (en) | 1999-07-27 | 1999-07-27 | Method for manufacturing semiconductor device |
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| KR (1) | KR100381399B1 (en) |
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| US6372601B1 (en) * | 1998-09-03 | 2002-04-16 | Micron Technology, Inc. | Isolation region forming methods |
| JP3983019B2 (en) * | 2001-08-24 | 2007-09-26 | シャープ株式会社 | Manufacturing method of substrate having embedded structure and manufacturing method of display device |
| KR20030049201A (en) * | 2001-12-14 | 2003-06-25 | 주식회사 하이닉스반도체 | Method for forming a isolation film of semiconductor device |
| KR20040000682A (en) * | 2002-06-25 | 2004-01-07 | 동부전자 주식회사 | Method for forming isolation layer of semiconductor device |
| KR100459929B1 (en) * | 2002-06-25 | 2004-12-03 | 동부전자 주식회사 | Method for forming isolation layer of semiconductor device |
| KR20040006320A (en) * | 2002-07-11 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for forming isolation layer of semiconductor device |
| KR100473731B1 (en) * | 2002-10-14 | 2005-03-10 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
| JP3871271B2 (en) | 2003-05-30 | 2007-01-24 | 沖電気工業株式会社 | Manufacturing method of semiconductor device |
| JP4947931B2 (en) | 2004-08-12 | 2012-06-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| KR100713316B1 (en) * | 2005-12-28 | 2007-05-04 | 동부일렉트로닉스 주식회사 | Method for dual isolation in semiconductor device |
| US7846812B2 (en) | 2007-12-18 | 2010-12-07 | Micron Technology, Inc. | Methods of forming trench isolation and methods of forming floating gate transistors |
| US8003482B2 (en) | 2009-11-19 | 2011-08-23 | Micron Technology, Inc. | Methods of processing semiconductor substrates in forming scribe line alignment marks |
| US9761520B2 (en) * | 2012-07-10 | 2017-09-12 | Hsio Technologies, Llc | Method of making an electrical connector having electrodeposited terminals |
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| KR0183854B1 (en) * | 1996-05-15 | 1999-04-15 | 김광호 | Trench element isolation method of semiconductor element |
-
1999
- 1999-07-27 JP JP21234199A patent/JP3439387B2/en not_active Expired - Fee Related
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