JP3270912B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3270912B2 JP3270912B2 JP04955994A JP4955994A JP3270912B2 JP 3270912 B2 JP3270912 B2 JP 3270912B2 JP 04955994 A JP04955994 A JP 04955994A JP 4955994 A JP4955994 A JP 4955994A JP 3270912 B2 JP3270912 B2 JP 3270912B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- insulating film
- side wall
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、改良された素子間分離
構造をもつ半導体装置を製造するのに好適な方法に関す
る。 BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method suitable for manufacturing a semiconductor device having an improved element isolation structure.
You.
【０００２】半導体装置の更なる高集積化を実現する
為、平面的な占有面積が少なく且つ信頼性が高い素子間
分離構造が希求され、それに応える一手段として、選択
エピタキシャル成長（ｓｅｌｅｃｔｉｖｅ ｅｐｉｔａ
ｘｉａｌ ｇｒｏｗｔｈ；ＳＥＧ）法を利用した素子間
分離技術が知られているが、未だ改良されなければなら
ない点を残している。[0002] In order to further increase the degree of integration of a semiconductor device, a highly reliable inter-element isolation structure having a small planar occupation area and high reliability has been demanded. As a means for meeting the demand, selective epitaxial growth (selective epita-
An element isolation technique using a xial growth (SEG) method is known, but it still needs to be improved.
【０００３】[0003]
【従来の技術】現在、ＳＥＧ法と呼ばれる素子間分離技
術には、次の二つの手段が良く知られている。2. Description of the Related Art At present, the following two means are well known as an element isolation technique called SEG method.
【０００４】 Ｓｉ基板上に形成されたＳｉＯ2 膜を
異方性エッチングして開口を形成し、その中にＳＥＧ法
に依るＳｉ膜を充填して活性領域とする方法。A method in which an opening is formed by anisotropically etching a SiO 2 film formed on a Si substrate, and a Si film is filled therein by the SEG method to form an active region.
【０００５】 Ｓｉ基板自体を異方性エッチングして
凹所を形成し、凹所側壁を絶縁膜で覆ってから、ＳＥＧ
法に依る低濃度ドーピングＳｉを凹所に充填して活性領
域とする方法（要すれば、「特開平４−１５９３５号公
報」、を参照）。A recess is formed by anisotropically etching the Si substrate itself, and the sidewall of the recess is covered with an insulating film.
A method in which a recess is filled with low-concentration doped Si according to a method to form an active region (refer to "Japanese Patent Application Laid-Open No. 4-15935", if necessary).
【０００６】[0006]
【発明が解決しようとする課題】ＳＥＧ法に依る素子間
分離技術のうち、前記については、ＳｉとＳｉＯ2 の
熱膨張率の相違から、Ｓｉ中に欠陥が発生し易い旨の問
題があり、また、前記については、Ｓｉ基板を異方性
エッチングして凹所を形成する際、反応性イオン・エッ
チング（ｒｅａｃｔｉｖｅ ｉｏｎ ｅｔｃｈｉｎｇ：
ＲＩＥ）法を適用するので、Ｓｉ基板がダメージを受け
る旨の問題がある。Among the element isolation techniques based on the SEG method, there is a problem that defects are easily generated in Si due to a difference in thermal expansion coefficient between Si and SiO 2 . In the above, when forming a recess by anisotropically etching a Si substrate, reactive ion etching (reactive ion etching:
Since the RIE method is applied, there is a problem that the Si substrate is damaged.
【０００７】本発明は、ＳＥＧ法に依る素子間分離を行
うに際し、簡単な手段に依って、欠陥発生の問題、及
び、Ｓｉ基板がダメージを受ける問題を解消しようとす
る。The present invention is intended to solve the problem of the occurrence of defects and the problem of damage to the Si substrate by simple means when performing element isolation by the SEG method.
【０００８】[0008]
【発明が解決しようとする課題】本発明では、素子間分
離部分を形成してから活性領域となるべき半導体層をエ
ピタキシャル成長させるのであるが、その間に結晶欠陥
の問題や基板がダメージを受ける問題は発生しない。According to the present invention, a semiconductor layer to be an active region is epitaxially grown after an element isolation portion is formed. During this period, the problem of crystal defects and the problem of damage to a substrate are encountered. Does not occur.
【０００９】[0009]
【００１０】[0010]
【００１１】本発明に依る半導体装置の製造方法に於い
ては、 （１） 半導体基板（ｐ型Ｓｉ基板１）表面の単結晶半導体活性
層形成予定部分上に順に積層されて突出する半導体膜
（多結晶Ｓｉ膜２）及び第一の絶縁膜（ＳｉＮ膜３）を
形成する工程と、次いで、前記第一の絶縁膜と同じ材質
であって前記突出する半導体膜及び第一の絶縁膜に於け
る側壁を覆うサイド・ウォール膜（ＳｉＮからなるサイ
ド・ウォール膜５）を形成する工程と、次いで、前記単
結晶半導体活性層形成予定部分を除く前記半導体基板表
面にノンドープ半導体層（ノンドープＳｉ層６）を形成
してから前記ノンドープ半導体層の表面を第二の絶縁膜
（ＳｉＯ2 からなる絶縁膜７）で覆う工程と、次いで、
第一の絶縁膜及び前記サイド・ウォール膜の一部を除去
して前記サイド・ウォール膜で囲まれた前記半導体膜の
表面を露出させる工程と、次いで、前記表面が露出され
た半導体膜を全て除去する工程と、次いで、前記サイド
・ウォール膜で囲まれてなる前記半導体膜が除去された
跡（凹所５Ａ）に単結晶半導体活性層（ｐ型Ｓｉ活性層
８）を形成する工程とが含まれてなることを特徴とする
か、或いは、In a method for manufacturing a semiconductor device according to the present invention,
Te is (1) a semiconductor film (polycrystalline Si film 2) projecting are laminated in this order on a semiconductor substrate (p-type Si substrate 1) surface of the single crystal semiconductor active layer to be formed on the portion and the first insulating film (SiN Forming a film 3), and then forming a side wall film (SiN) made of the same material as the first insulating film and covering the protruding semiconductor film and the side wall of the first insulating film. Forming a wall film 5), and then forming a non-doped semiconductor layer (non-doped Si layer 6) on the surface of the semiconductor substrate except for the portion where the single crystal semiconductor active layer is to be formed, and then changing the surface of the non-doped semiconductor layer to a second Covering with a second insulating film (insulating film 7 made of SiO 2 );
Removing the first insulating film and part of the side wall film to expose the surface of the semiconductor film surrounded by the side wall film, and then removing all of the semiconductor film having the exposed surface. The step of removing and then the step of forming a single-crystal semiconductor active layer (p-type Si active layer 8) at the mark (recess 5A) where the semiconductor film surrounded by the side wall film has been removed. Is characterized by being included, or
【００１２】（２） 前記（１）に於いて、第一の絶縁膜が窒化膜及び第二の
絶縁膜が酸化膜であることを特徴とするか、或いは、 (2) In the above (1) , the first insulating film is a nitride film and the second insulating film is an oxide film, or
【００１３】（３） 前記（１）或いは（２）に於いて、単結晶半導体活性層
形成予定部分を除く半導体基板表面にノンドープ半導体
層を形成してから表面を酸化して第二の絶縁膜を形成す
る工程が含まれてなることを特徴とする。 (3) In the above (1) or (2) , a non-doped semiconductor layer is formed on the surface of the semiconductor substrate except for a portion where a single crystal semiconductor active layer is to be formed, and then the surface is oxidized to form a second insulating film. Is formed.
【００１４】[0014]
【作用】前記手段を採ることに依り、熱膨張係数を異に
する絶縁膜中に活性領域を形成するものではないことか
ら、活性領域を構成する半導体に欠陥が発生することは
ない。また、基板自体に対してＲＩＥ法に依るエッチン
グを加えることはないから、基板にダメージを与えるこ
とはない。更にまた、ＳＥＧ及び熱酸化は自己整合的に
行うことができるからマスク工程は一回で済み、Ｓｉ層
や絶縁膜の厚さ調整は容易であることから平坦性も良好
である。According to the above means, no active region is formed in an insulating film having a different coefficient of thermal expansion. Therefore, no defect occurs in the semiconductor constituting the active region. Further, since the etching of the substrate itself by the RIE method is not performed, the substrate is not damaged. Furthermore, since the SEG and the thermal oxidation can be performed in a self-aligned manner, only one mask process is required, and the thickness of the Si layer and the insulating film can be easily adjusted, so that the flatness is good.
【００１５】[0015]
【実施例】図１乃至図８は本発明一実施例を説明する為
の工程要所に於ける半導体装置の要部切断側面図であ
り、以下、これ等の図を参照しつつ説明する。1 to 8 are cutaway side views of a principal part of a semiconductor device in a process step for explaining an embodiment of the present invention, and the description will be made with reference to these drawings.
【００１６】図１参照 １−（１）化学気相堆積（ｃｈｅｍｉｃａｌ ｖａｐｏ
ｕｒ ｄｅｐｏｓｉｔｉｏｎ：ＣＶＤ）法を適用するこ
とに依って、ｐ型Ｓｉ基板１上に厚さ例えば１０００
〔Å〕程度の多結晶Ｓｉ膜２を形成する。Referring to FIG. 1, 1- (1) chemical vapor deposition (chemical vapor deposition)
ur deposition (CVD) method, a thickness of, for example, 1000
[Å] Polycrystalline Si film 2 is formed.
【００１７】１−（２）同じく、ＣＶＤ法を適用するこ
とに依って、多結晶Ｓｉ膜２上に厚さ例えば３００
〔Å〕のＳｉＮ膜３を形成する。1- (2) Similarly, by applying the CVD method, a thickness of, for example, 300
[Å] The SiN film 3 is formed.
【００１８】１−（３）リソグラフィ技術に於けるレジ
スト・プロセスを適用することに依って、活性層形成予
定部分を覆うレジスト膜４を形成する。1- (3) A resist film 4 is formed to cover a portion where an active layer is to be formed by applying a resist process in a lithography technique.
【００１９】図２参照 ２−（１）エッチング・ガスをＣＨＦ3 或いはＣＦ
4 （ＳｉＮ用）並びにＨＢｒ（多結晶Ｓｉ用）とするＲ
ＩＥ法を適用することに依って、ＳｉＮ膜３並びに多結
晶Ｓｉ膜２のエッチングを行う。FIG. 2 2- (1) CHF 3 or CF etching gas
4 R (for SiN) and HBr (for polycrystalline Si)
The SiN film 3 and the polycrystalline Si film 2 are etched by applying the IE method.
【００２０】２−（２）ＣＶＤ法を適用することに依っ
て、厚さ例えば３００〔Å〕程度のＳｉＮ膜を形成す
る。2- (2) A SiN film having a thickness of, for example, about 300 [Å] is formed by applying the CVD method.
【００２１】図３参照 ３−（１）エッチング・ガスをＣＨＦ3 或いはＣＦ4 と
するＲＩＥ法を適用することに依って、ＳｉＮ膜の異方
性エッチングを行い、多結晶Ｓｉ膜２及びＳｉＮ膜３の
側壁にＳｉＮからなるサイド・ウォール膜５を形成す
る。ここで、サイド・ウォール膜５、ＳｉＮ膜３、多結
晶Ｓｉ膜２は活性層形成予定部分を覆っている。Referring to FIG. 3, 3- (1) anisotropic etching of the SiN film is performed by applying the RIE method using CHF 3 or CF 4 as an etching gas, so that the polycrystalline Si film 2 and the SiN film are formed. A side wall film 5 made of SiN is formed on the side wall 3. Here, the side wall film 5, the SiN film 3, and the polycrystalline Si film 2 cover the portion where the active layer is to be formed.
【００２２】図４参照 ４−（１）ＳＥＧ法を適用することに依り、表出されて
いるＳｉ基板１上に厚さ例えば７００〔Å〕のノンドー
プＳｉ層６をエピタキシャル成長させる。Referring to FIG. 4, a non-doped Si layer 6 having a thickness of, for example, 700 [Å] is epitaxially grown on the exposed Si substrate 1 by applying the 4- (1) SEG method.
【００２３】図５参照 ５−（１）温度９００〔℃〕、時間２５〔分〕の熱処理
を行って、ノンドープＳｉ層６の表面に厚さ約５００
〔Å〕のＳｉＯ2 からなる絶縁膜７を形成する。ノンド
ープＳｉ層６の厚さ及び絶縁膜７の厚さを前記の値にす
ると、この場合、その表面が多結晶Ｓｉ膜２の表面と略
等しくなる。Referring to FIG. 5, 5- (1) heat treatment is performed at a temperature of 900 ° C. for a time of 25 minutes to form a film having a thickness of about 500 on the surface of the non-doped Si layer 6.
[Å] The insulating film 7 made of SiO 2 is formed. When the thickness of the non-doped Si layer 6 and the thickness of the insulating film 7 are set to the above-mentioned values, in this case, the surface thereof is substantially equal to the surface of the polycrystalline Si film 2.
【００２４】図６参照 ６−（１）エッチング・ガスをＣＨＦ3 ＋ＣＦ4 とする
ＲＩＥ法を適用することに依って、サイド・ウォール膜
５の一部とＳｉＮ膜３をエッチ・バックし、多結晶Ｓｉ
膜２を表出させる。尚、このエッチ・バックは、多結晶
Ｓｉ膜２が表出した時点で自動的に停止する。FIG. 6 6- (1) A part of the side wall film 5 and the SiN film 3 are etched back by applying the RIE method using CHF 3 + CF 4 as an etching gas. Crystal Si
The membrane 2 is exposed. The etch back automatically stops when the polycrystalline Si film 2 is exposed.
【００２５】図７参照 ７−（１）ＨＣｌＯ4 ：Ｈ3 ＰＯ4 ：ＨＮＯ4 ：ＨＦ＝
６０：１５：５：１からなるエッチャント中に浸漬し、
多結晶Ｓｉ膜２を除去してＳｉＮ膜３で囲まれた活性層
形成予定部分である凹所５Ａの底にＳｉ基板１の一部表
面を露出させる。See FIG. 7 7- (1) HClO 4 : H 3 PO 4 : HNO 4 : HF =
Immersed in an etchant consisting of 60: 15: 5: 1
The polycrystalline Si film 2 is removed, and a part of the surface of the Si substrate 1 is exposed at the bottom of the recess 5A which is a portion where the active layer is to be formed and is surrounded by the SiN film 3.
【００２６】図８参照 ８−（１）ＳＥＧ法を適用することに依り、凹所５Ａを
埋めるｐ型Ｓｉ活性層８を形成する。尚、この場合で
は、ｐ型Ｓｉ活性層８の厚さは約１０００〔Å〕程度に
すると凹所５Ａは完全に埋まる。Referring to FIG. 8, 8- (1) p-type Si active layer 8 filling recess 5A is formed by applying the SEG method. In this case, when the thickness of the p-type Si active layer 8 is about 1000 [Å], the recess 5A is completely filled.
【００２７】８−（２）この後、通常の技法を適用する
ことに依り、ｐ型Ｓｉ活性層８にＭＩＳ−ＦＥＴ（ｍｅ
ｔａｌ ｉｎｓｕｌａｔｏｒ ｓｅｍｉｃｏｎｄｕｃｔ
ｏｒ−ｆｉｅｌｄ ｅｆｆｅｃｔ ｔｒａｎｓｉｓｔｏ
ｒ）やバイポーラ・トランジスタを作り込めば良い。8- (2) After that, the MIS-FET (me
tal insulator semiconductor
or-field effect transisto
r) and bipolar transistors.
【００２８】[0028]
【発明の効果】本発明に依る半導体装置の製造方法に於
いては、半導体基板表面に突出し且つ周囲が第一の絶縁
膜で囲まれた単結晶半導体活性層が形成され、第一の絶
縁膜を介して単結晶半導体活性層を囲むノンドープ半導
体層及びその上の第二の絶縁膜からなる積層体が形成さ
れる。Is In the manufacturing method of a semiconductor device according to the present invention, the single crystal semiconductor active layer and the surrounding protruding semiconductor substrate surface surrounded by the first insulating film is formed, a first insulation A stacked body including the non-doped semiconductor layer surrounding the single-crystal semiconductor active layer via the edge film and the second insulating film thereon is formed.
【００２９】前記構成を採ることに依り、熱膨張係数を
異にする絶縁膜中に活性領域を形成するものではないこ
とから、活性領域を構成する半導体に欠陥が発生するこ
とはない。また、基板自体に対してＲＩＥ法に依るエッ
チングを加えることはないから、基板にダメージを与え
ることはない。更にまた、ＳＥＧ及び熱酸化は自己整合
的に行うことができるからマスク工程は一回で済み、Ｓ
ｉ層や絶縁膜の厚さ調整は容易であることから平坦性も
良好である。According to the above configuration, since the active region is not formed in the insulating films having different thermal expansion coefficients, no defect occurs in the semiconductor constituting the active region. Further, since the etching of the substrate itself by the RIE method is not performed, the substrate is not damaged. Furthermore, since SEG and thermal oxidation can be performed in a self-aligned manner, only one mask step is required,
Since the thickness adjustment of the i-layer and the insulating film is easy, the flatness is also good.
【図１】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 1 is a cutaway side view of a main part of a semiconductor device in a process key point for explaining an embodiment of the present invention.
【図２】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 2 is a cross-sectional side view of a main part of the semiconductor device at a key point in a process for explaining one embodiment of the present invention;
【図３】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 3 is a cutaway side view of a main part of a semiconductor device in a process key point for explaining an embodiment of the present invention.
【図４】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 4 is a cutaway side view of a main part of a semiconductor device at a key point in a process for explaining one embodiment of the present invention;
【図５】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 5 is a cutaway side view of a main part of a semiconductor device at a key point in a process for explaining one embodiment of the present invention;
【図６】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 6 is a cutaway side view of a main part of a semiconductor device at a key point in a process for explaining one embodiment of the present invention;
【図７】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 7 is a cutaway side view of a main part of a semiconductor device at a key point in a process for explaining one embodiment of the present invention;
【図８】本発明一実施例を説明する為の工程要所に於け
る半導体装置の要部切断側面図である。FIG. 8 is a cutaway side view of a main part of a semiconductor device at a key point in a process for explaining one embodiment of the present invention;
１ ｐ型Ｓｉ基板 ２ 多結晶Ｓｉ膜 ３ ＳｉＮ膜 ４ レジスト膜 ５ サイド・ウォール膜 ６ ノンドープＳｉ層 ７ ＳｉＯ2 からなる絶縁膜 ５Ａ 凹所Reference Signs List 1 p-type Si substrate 2 polycrystalline Si film 3 SiN film 4 resist film 5 side wall film 6 non-doped Si layer 7 insulating film made of SiO 2 5A recess
Claims (3)
予定部分上に順に積層されて突出する半導体膜及び第一
の絶縁膜を形成する工程と、 次いで、前記第一の絶縁膜と同じ材質であって前記突出
する半導体膜及び第一の絶縁膜に於ける側壁を覆うサイ
ド・ウォール膜を形成する工程と、 次いで、前記単結晶半導体活性層形成予定部分を除く前
記半導体基板表面にノンドープ半導体層を形成してから
前記ノンドープ半導体層の表面を第二の絶縁膜で覆う工
程と、 次いで、第一の絶縁膜及び前記サイド・ウォール膜の一
部を除去して前記サイド・ウォール膜で囲まれた前記半
導体膜の表面を露出させる工程と、 次いで、前記表面が露出された半導体膜を全て除去する
工程と、 次いで、前記サイド・ウォール膜で囲まれてなる前記半
導体膜が除去された跡に単結晶半導体活性層を形成する
工程とが含まれてなることを特徴とする半導体装置の製
造方法。 1. Formation of a single crystal semiconductor active layer on a surface of a semiconductor substrate
A first semiconductor film and a first semiconductor film stacked and projected on a predetermined portion in order;
Forming an insulating film, and then forming the same material as the first insulating film,
Covering the side wall of the semiconductor film and the first insulating film
Forming a doped wall film, and then before removing a portion where the single crystal semiconductor active layer is to be formed.
After forming a non-doped semiconductor layer on the surface of the semiconductor substrate
Covering the surface of the non-doped semiconductor layer with a second insulating film
And then one of the first insulating film and the side wall film.
The half surrounded by the side wall film is removed.
A step of exposing the surface of the conductive film, and then removing all the semiconductor film having the exposed surface
Step, and then the half formed by the side wall film.
Form a single-crystal semiconductor active layer at the mark where the conductor film has been removed
Manufacturing a semiconductor device, comprising:
Construction method.
酸化膜であることを特徴とする請求項１記載の半導体装
置の製造方法。 2. The method according to claim 1, wherein the first insulating film is a nitride film and the second insulating film is a nitride film.
2. The semiconductor device according to claim 1, wherein the semiconductor device is an oxide film.
Manufacturing method of the device.
導体基板表面にノンドープ半導体層を形成してから表面
を酸化して第二の絶縁膜を形成する工程が含まれてなる
ことを特徴とする請求項１或いは請求項２記載の半導体
装置の製造方法。 3. A half excluding a portion where a single crystal semiconductor active layer is to be formed.
After forming a non-doped semiconductor layer on the conductor substrate surface,
Oxidizing to form a second insulating film
The semiconductor according to claim 1 or 2, wherein
Device manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04955994A JP3270912B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04955994A JP3270912B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07263533A JPH07263533A (en) | 1995-10-13 |
| JP3270912B2 true JP3270912B2 (en) | 2002-04-02 |
Family
ID=12834567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04955994A Expired - Lifetime JP3270912B2 (en) | 1994-03-18 | 1994-03-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3270912B2 (en) |
-
1994
- 1994-03-18 JP JP04955994A patent/JP3270912B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07263533A (en) | 1995-10-13 |
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