JPS5882532A - Element separation method - Google Patents

Abstract

PURPOSE:To separate a flat substrate surface by a buried layer by providing vertical grooves on the Si substrate, depositing therein a poly Si film through an insulation film and removing said insulation film and poly Si on the surface by the anisotropic etching. CONSTITUTION:Vertical grooves 4 are provided on a Si substrate 5 by the reactive ion etching using a resist mask 6 and the boron B ion is then implanted. The resist is removed, the surface is covered with the SiO27 film and an inversion preventing layer 8 is formed. A poly Si layer 3 is deposited, the phosphorus P is diffused, a film 3 is anisotropically processed by the reactive ion etching, thereby the SiO27 becomes a stopper and the poly Si 3' is left within the grooves 4 and the poly Si3 is removed from the surface. This film 7 is removed and the surface is newly covered with the SiO2 film 7. Thus, a separation region 9 is completed and the surface becomes flat. According to this method, an element separation region is obtained at a low temperature, the separation region and separation interface become flat allowing multi-layer wirings and not generating fault due to stress. Thereby a microminiaturized device can be completed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device isolation method using anisotropic processing.

A local oxidation method using silicon nitride is generally known as a device isolation method for semiconductor integrated circuits. However, this method has the following problem of forming a thick thermal oxide film for element isolation.

■Impurity O in the embedding layer and surface inversion prevention layer during high-temperature heat treatment
redistribution occurs; ■ a steep convex portion called 1A-ohe, do1 occurs on the outer part of the separation interface, leading to disconnection of the wiring; a multilayer wiring structure is adopted; There is a limit to the miniaturization of devices due to the formation of thin oxide film regions called 1-birds-V-ri 1, and the fact that silicon nitride is used to prevent scratches from forming between the silicon nitride and the semiconductor substrate. There were various drawbacks such as causing defective OJ.

RIE the silicon film (R@agtlv* Ion E
We have discovered a phenomenon in which the polycrystalline silicon film remains on the stepped portion without being etched when anisotropically etched using the etching method.

To explain this phenomenon with reference to FIGS. 1 to 3, first, as shown in FIG. 1, a 1ft step is formed on the surface of the semiconductor substrate 10, and then a polycrystalline silicon film 3 with a thickness t is deposited on the entire surface by a reduced pressure method. . Next, use CCt4 as a starting point and R
When etched from the surface using the IE method, a polycrystalline silicon film 3' remains at the stepped portion 2 with a thickness of t and a height approximately equal to the width of the stepped portion 2, as shown in FIG.

The reason for this is thought to be that some portion remains due to a combination of conditions, such as step portion 2 being vertical, polycrystalline silicon film 3 being deposited in the same direction, and etching proceeding only from the top surface.

Further, by utilizing the above phenomenon, as shown in FIG. 3, a groove 4t is formed in the semiconductor substrate 1, the inner wall of which is perpendicular to the substrate surface, has a width W1 and a depth d, and has a thickness t such that t>W. When the polycrystalline silicon film 3 is deposited on the entire surface so as to have a thickness of /2, the polycrystalline silicon film 3 is also buried in the trench 4. Next, when anisotropic processing is performed using the RIE method, the polycrystalline silicon film J deposited on the substrate surface other than the groove portion 4 is removed, and an isolation region with a flat surface is formed in the substrate.

The present invention has been made based on the above findings, and it is possible to form an element isolation region at a low temperature by leaving deposits in the groove portion by anisotropic processing, and also to form an isolation region on the surface of the element isolation region and the isolation interface. An element isolation method that enables multi-layer interconnection by flattening the wiring (which enables high-density integration by making it possible to miniaturize elements), and also prevents defects due to stress and improves device reliability. It provides:

That is, the method of the present invention includes the steps of forming a groove portion whose inner wall is perpendicular to the substrate surface in a portion of a semiconductor substrate where an element isolation region is to be formed, and forming a polycrystalline silicon film over the entire surface of the substrate via an insulating material. Alternatively, the polycrystalline silicon film deposited on the surface of the substrate other than the one injected into the groove by anisotropic processing and the step of directly depositing an insulating material may be removed.
M! The method is characterized by comprising the steps of smoothing the surface and injecting mo1g and separating the moieties over the entire area.

The method of the present invention will be explained in detail below.

In the present invention, an ore, a polycrystalline silicon film, or an insulating film is used as a film deposited over the entire surface of a partially formed semiconductor substrate. When a polycrystalline silicon film is used, it must be deposited through an insulating film because it is conductive. Further, in order to increase the rate of thermal oxidation in the polycrystalline silicon/film, adjacent impurities may be thermally diffused, or an adjacently doped polycrystalline silicon film may be used.

The insulating film to be deposited may be a silicon oxide film, a silicon oxide film, or an alumina film, and the silicon oxide film may be deposited by CVD or by thermal oxidation growth. When these insulating films are used, they can be deposited directly on the substrate surface.

The anti-inversion layer formed under the element isolation region is not limited to the method of forming the trench by ion implantation after forming the trench, but may also be formed by forming an impurity region in advance and using it as a buried layer.

Note that the method of the present invention can be applied not only to bipolar devices but also to element isolation of MOa type semiconductor devices.

Next, an embodiment will be described in which the present invention is used to optimize the m5 of Pyra WNPN) Lanzosta.

Sections 4 to 91I are 11K in which one embodiment of the present invention is sequentially constructed.
I! This is what is shown.

First, as shown in No. 411, the silicon:I substrate 5 is coated with a photoresist, and then RImCv is applied to the portion where the element isolation region will be formed so as to surround the active region.
Width W 2 fims Depth 1d 1.5-2, OA
() Form a groove 4 whose inner wall is perpendicular to the substrate surface.Next, using the patterned photoresist # as a master, ion implantation is performed into the lower part of the groove 4. The ion implantation conditions at this time are an acceleration voltage of 1110 K@T
, The dose was 1X10''/d.

Next, remove the photoresist C, and then remove the silicon substrate IOI.
! l! The surface is oxidized to a thickness of 14,000~ as shown in Figure 5.
5ooolo silicone oxide film yl is formed・At this time,
The first injected straw is activated at the same time, and Hisashi 1140T
A IIK anti-inversion layer I is formed.

Next, as shown in Fig. 6, the thickness t was reduced to 1μ by a vacuum method.
A polycrystalline silicon film Jt of m is deposited on the entire surface. In this case, since the width W of the groove 40 is 2 μm, the polycrystalline silicon film S is completely filled with the groove 4f. Next, in order to increase the rate of thermal oxidation of the polycrystalline silicon film S in the subsequent process,
Adjacent thermal diffusion is performed on the polycrystalline silicon film 3 using POCjg.

Next, a polycrystalline silicon film 1 is formed on the substrate surface using the RIE method.
Then, as shown in FIG. 7, anisotropic processing is performed. As a result, the silicon oxide film r formed on the substrate surface acts as an etching stopper, the polycrystalline silicon film 3' buried in the groove 4 remains as it is, and the other polycrystalline silicon film 3 on the substrate surface 0 Next, the silicon oxide film r exposed on the surface is removed. 6 Next, the surface of the remaining polycrystalline silicon film S' buried in the first trench 4 is thermally oxidized again as shown in FIG. Thickness approximately 50001.
A silicon/oxide film 1 with a thickness of approximately 2000× is simultaneously formed on the surface of the silicon substrate SO. As a result, the periphery of the remaining polycrystalline silicon III' buried in the trench s4 is covered and insulated with a silicon oxide film r, and a buried 11O element isolation region 9 whose surface and isolation interface are flattened is formed.

Hereinafter, according to the usual Ofl process, the a-sliding required area 10 is formed by the element isolation region, ti,; buried layer 11,
Amarinori C taxial layer 12, ♀ type base region 11. and N+ mold work 1. Evening area 14, Preta! Removal area 15f
: Formed as shown in FIG.
Manufacture Funjista.

Accordingly, the above method requires fewer high-temperature heat treatment steps than the conventional device isolation method using silicon nitride by zero local oxidation, making it easier to prevent impurity redistribution. t
1/ Since the electrode head 1 does not occur and the surface of the element isolation region 90 is flattened to the same level as the surface of the silicon substrate 50, there is no disconnection of wiring and multilayer wiring is easy.
Moreover, the isolation interface is also flattened and no "1 bird's beak" occurs, allowing the device to be miniaturized.Furthermore, unlike conventional silicon nitride, silicon nitride is not used, so there is stress between the separation interface and the silicon substrate 5, which can cause defects. It is possible to obtain a product with excellent reliability without the occurrence of.

In the above embodiment, the relationship between the thickness t of the polycrystalline silicon film 3 and the width W of the groove portion 4 is t'2-W/2, but on the contrary, the relationship t<W/2 is shown. Let me explain the case.

In this case, as shown in FIG.
When the polycrystalline silicon film 3 is deposited in this manner, the inside of the trench 4 is not completely filled with the polycrystalline silicon film 3 and becomes hollow.

After this, the polycrystalline silicon film 3 other than the groove portion 4 is etched by RIE method to perform anisotropic processing, and then reoxidized to form a thick silicon oxide film 1 on the surface of the polycrystalline silicon film J.
11), the inside of the tc11 portion 4 is completely KJI-filled, forming an element isolation region 9 with a flat surface.

In addition, in the above embodiment, when the polycrystalline silicon film 3 is deposited to separate elements, the problem is that 8≦0□ is an insulating film.
Next, the case of device isolation by depositing a film will be described.

As shown in FIG. 12, the width W of the groove 4 is set to 1411, for example.
1, and the depth is di-2 μm.

The silicon-based gmop surface is thermally oxidized to 810. When the film IC is grown and deposited to a thickness t m 11kyn, the trench 4
Oxidation proceeds from three directions and is completely buried with the 8102 film II, creating a hole for forming an element isolation region p with a flat surface.

Therefore, with this method, the width of the element isolation region 90 can be further narrowed, and high-density integration can be achieved.

As explained above, according to the device isolation method according to the present invention, the device isolation region can be formed at a low temperature by leaving the deposits in the groove portion by anisotropic processing, and the surface of the device isolation region and the isolation interface can be formed. This enables multi-layer interconnection by flattening the metal layer, and enables miniaturization of the elements to achieve high-density deposition.
This has remarkable effects such as being able to prevent the occurrence of defects due to stress and improve the reliability of the device.

[Brief explanation of drawings]

FIGS. 1 to 3 are cross-sectional views explaining the phenomenon of deposits remaining due to anisotropic processing, and FIGS. 4 to 9 are cross-sectional views explaining the present invention.
- Cross-sectional view showing the manufacture of a Laya transistor, Figure 12B
FIG. 3 is a cross-sectional view of the case where a silicon element isolation region is formed using a 5so2 film. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Step part, J-...Polycrystalline silicon film, 3'...Remaining polycrystalline silicon film, 4-...
-Groove portion, 5...Silicon substrate, 6...Photoresist, 7...Lean oxide film, 8--Inversion prevention layer, 9--
Element isolation region, 10...active region, 16...8tO
fi membrane applicant patent attorney Suzue Takehiko 8 8 11 12 8

Claims (1)

[Claims] A process of forming a groove portion whose inner wall is almost perpendicular to the substrate surface in a portion of a semiconductor substrate where an element isolation region is to be formed, and a process of depositing a polycrystalline silicon film or a direct insulating film over the entire surface of the substrate via an insulating film. and a step of flattening the substrate surface by removing the polycrystalline silicon film or insulating film deposited on the substrate surface other than that buried in the groove by anisotropic processing, and forming a buried element isolation region. Consisting of′@：
Characteristic element isolation method.