JPS5654049A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5654049A
JPS5654049A JP13038079A JP13038079A JPS5654049A JP S5654049 A JPS5654049 A JP S5654049A JP 13038079 A JP13038079 A JP 13038079A JP 13038079 A JP13038079 A JP 13038079A JP S5654049 A JPS5654049 A JP S5654049A
Authority
JP
Japan
Prior art keywords
film
groove
sio
flat surface
cvd method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13038079A
Other languages
Japanese (ja)
Inventor
Natsuo Tsubouchi
Masahiro Yoneda
Koichi Nagasawa
Hiroji Harada
Katsuhiro Hirata
Masahiko Denda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13038079A priority Critical patent/JPS5654049A/en
Priority to DE19803038067 priority patent/DE3038067A1/en
Publication of JPS5654049A publication Critical patent/JPS5654049A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE: To obtain a separation groove with a flat surface in a small area by stacking an Si3N4 film in a groove between circuit elements.
CONSTITUTION: An N+ layer 2 is made on a P type substrate 1 and an N epitaxial layer 3 is grown thereon. With an SiO2 maks 4, a vertical separation groove is produced by reactive ion etching. Then, an SiO2 thin film 6 is formed on the inner surface of the groove by thermal oxidization while a channel cut is made onthe bottom with the implantation of B ion. An Si3N4 7 is formed from a gas mixture of SiH2Cl2, NH3 and N2 by decompression CVD method to bury the groove. As the film 7 is stacked through surface reaction, it grows faithful to the surface and buried almost flat to thereof. No flat surface can not be obtained by nromal pressure CVD method. Then, the Si3N4 film 7 is etched away until an SiO2 film 4 is exposed. Thereafter, the semiconductor is formed as in the past. With such an arrangement, a separation construction between elements is obtained with a flat surface in a small area. The quick low temperature formation thereof eliminates redistribution of the diffusion and induced lack of crystal.
COPYRIGHT: (C)1981,JPO&Japio
JP13038079A 1979-10-09 1979-10-09 Semiconductor device Pending JPS5654049A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP13038079A JPS5654049A (en) 1979-10-09 1979-10-09 Semiconductor device
DE19803038067 DE3038067A1 (en) 1979-10-09 1980-10-08 Semiconductor insulator or separator - has groove extending to substrate and filled with silicon nitride produced rapidly at low temp. and giving planar surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13038079A JPS5654049A (en) 1979-10-09 1979-10-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5654049A true JPS5654049A (en) 1981-05-13

Family

ID=15032948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13038079A Pending JPS5654049A (en) 1979-10-09 1979-10-09 Semiconductor device

Country Status (2)

Country Link
JP (1) JPS5654049A (en)
DE (1) DE3038067A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771987U (en) * 1980-10-17 1982-05-01
JPS5848936A (en) * 1981-09-10 1983-03-23 Fujitsu Ltd Preparation of semiconductor device
JPS5882532A (en) * 1981-11-11 1983-05-18 Toshiba Corp Element separation method
JPS61239641A (en) * 1985-04-16 1986-10-24 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPH0199233A (en) * 1987-10-13 1989-04-18 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2017174902A (en) * 2016-03-22 2017-09-28 東京エレクトロン株式会社 Manufacturing method of semiconductor device and manufacturing system of semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119848A (en) * 1982-12-27 1984-07-11 Fujitsu Ltd Manufacture of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771987U (en) * 1980-10-17 1982-05-01
JPS6115428Y2 (en) * 1980-10-17 1986-05-13
JPS5848936A (en) * 1981-09-10 1983-03-23 Fujitsu Ltd Preparation of semiconductor device
JPS6229905B2 (en) * 1981-09-10 1987-06-29 Fujitsu Ltd
JPS5882532A (en) * 1981-11-11 1983-05-18 Toshiba Corp Element separation method
JPS61239641A (en) * 1985-04-16 1986-10-24 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPH0199233A (en) * 1987-10-13 1989-04-18 Fujitsu Ltd Semiconductor device and manufacture thereof
JP2017174902A (en) * 2016-03-22 2017-09-28 東京エレクトロン株式会社 Manufacturing method of semiconductor device and manufacturing system of semiconductor device

Also Published As

Publication number Publication date
DE3038067A1 (en) 1981-04-23

Similar Documents

Publication Publication Date Title
US4139442A (en) Reactive ion etching method for producing deep dielectric isolation in silicon
US4948456A (en) Confined lateral selective epitaxial growth
US4900689A (en) Method of fabrication of isolated islands for complementary bipolar devices
JPS54157485A (en) Planar semiconductor device
JPS5654049A (en) Semiconductor device
EP0206445A2 (en) Process for forming a semiconductor cell in a silicon semiconductor body and a mixed CMOS/bipolar integrated circuit formed in a plurality of such cells
JPS5756942A (en) Manufacture of silicon semiconductor device
JPS5624937A (en) Manufacture of semiconductor device
JPS5495185A (en) Production of semiconductor device
JPS58200554A (en) Manufacture of semiconductor device
JPS6457641A (en) Manufacture of semiconductor device
JPS5543882A (en) Gaseous-phase growing of compound semiconductor epitaxial film
JPS57196793A (en) Epitaxial growth method
JPS57192017A (en) Epitaxial growing method
JPS5721814A (en) Manufacture of semiconductor device
JPS57115822A (en) Manufacture of semiconductor device
JPS5591815A (en) Silicon epitaxial growth
KR100268901B1 (en) Method for forming field region of semiconductor device
JPS5499577A (en) Semiconductor assembly
JPS57196794A (en) Epitaxial growth method
JPS56133864A (en) Semiconductor device and manufacture thereof
JPS5499583A (en) Isolation method for semiconductor region
JPS5323559A (en) Production of compound semiconductor
JPS5550657A (en) Preparation of semiconductor device
JPS5350687A (en) Production of semiconductor device