JPS56133864A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS56133864A JPS56133864A JP3577580A JP3577580A JPS56133864A JP S56133864 A JPS56133864 A JP S56133864A JP 3577580 A JP3577580 A JP 3577580A JP 3577580 A JP3577580 A JP 3577580A JP S56133864 A JPS56133864 A JP S56133864A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- emitter
- region
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
PURPOSE:To reduce the base resistance and the emitter wiring resistance and obtain an element which is minuter and of higher performance and higher degree of integration by forming a base contact hole and an emitter region selectively by using the epitaxial growth technique and in the self alignment manner. CONSTITUTION:In the n<+> type burried layer in a p<-> type semiconductor substrate 1, a collector region 22 is provided, and n type epitaxial layer 3 is formed, and the N type semiconductor layer is isolated by a p<+> type isolation 4. Then, a portion of an Si nitride film 71 is opened to form a P type region 5 to be a base, and an Si nitride film 82 thereon is opened to grow undoped monocrystalline and polycrystalline Si layers 101 and 91 by using the vapor phase epitaxy to obtain the projecting layer 101 and the continuous layer 91 for the emitter leading electrode wiring. Then, an n<+> layer 102 is formed, the monocrystalline and polycrystalline Si layers are selectively oxidized, and the film 8 is removed by dry etching to form a base contact hole and an emitter region by the self alignment manner. Thereafter, a metal electrode film 11 is cover-attached thereto to obtain a bi-polar npn transistor of high speed and high degree of integration.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3577580A JPS56133864A (en) | 1980-03-22 | 1980-03-22 | Semiconductor device and manufacture thereof |
EP19810101993 EP0036620B1 (en) | 1980-03-22 | 1981-03-17 | Semiconductor device and method for fabricating the same |
DE8181101993T DE3160917D1 (en) | 1980-03-22 | 1981-03-17 | Semiconductor device and method for fabricating the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3577580A JPS56133864A (en) | 1980-03-22 | 1980-03-22 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56133864A true JPS56133864A (en) | 1981-10-20 |
Family
ID=12451253
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3577580A Pending JPS56133864A (en) | 1980-03-22 | 1980-03-22 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56133864A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61201465A (en) * | 1985-03-04 | 1986-09-06 | Nec Corp | Manufacture of transistor |
US5198689A (en) * | 1988-11-30 | 1993-03-30 | Fujitsu Limited | Heterojunction bipolar transistor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5029184A (en) * | 1973-07-17 | 1975-03-25 | ||
JPS52117579A (en) * | 1976-03-30 | 1977-10-03 | Nec Corp | Semiconductor device |
JPS52146574A (en) * | 1976-05-31 | 1977-12-06 | Sony Corp | Semiconductor device |
-
1980
- 1980-03-22 JP JP3577580A patent/JPS56133864A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5029184A (en) * | 1973-07-17 | 1975-03-25 | ||
JPS52117579A (en) * | 1976-03-30 | 1977-10-03 | Nec Corp | Semiconductor device |
JPS52146574A (en) * | 1976-05-31 | 1977-12-06 | Sony Corp | Semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61201465A (en) * | 1985-03-04 | 1986-09-06 | Nec Corp | Manufacture of transistor |
US5198689A (en) * | 1988-11-30 | 1993-03-30 | Fujitsu Limited | Heterojunction bipolar transistor |
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