JPS6453454A - Bipolar transistor and manufacture thereof - Google Patents

Bipolar transistor and manufacture thereof

Info

Publication number
JPS6453454A
JPS6453454A JP12884588A JP12884588A JPS6453454A JP S6453454 A JPS6453454 A JP S6453454A JP 12884588 A JP12884588 A JP 12884588A JP 12884588 A JP12884588 A JP 12884588A JP S6453454 A JPS6453454 A JP S6453454A
Authority
JP
Japan
Prior art keywords
polycrystalline silicon
grow
film
window
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12884588A
Other languages
Japanese (ja)
Other versions
JP2540912B2 (en
Inventor
Junzo Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of JPS6453454A publication Critical patent/JPS6453454A/en
Application granted granted Critical
Publication of JP2540912B2 publication Critical patent/JP2540912B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form both a base region and an emitter region so as to be selfaligned with a first window, so that the base region and the emitter region are made small in area by a method wherein a sidewall is formed inside a first window opened through a lithography technique. CONSTITUTION:A first polycrystalline silicon 6 and a first insulating 5, which are formed on a semiconductor substrate that comprises an n<+>-type buried layer 2 and an n-type epitaxial layer 3 formed on a p-type semiconductor substrate 1, are successively subjected to an anisotropic etching for the opening of a first window 9. The exposed surface of the n-type epitaxial layer 3 is oxidized and a silicon nitride film is subjected to etching so as to remove a first side wall 9a. Next, a second polycrystalline silicon film 12 is made to grow. A sixth insulating film 17 formed of the same silicon nitride film as a second side wall 14 is made to grow to be excellent in a step coverage, thereafter a third polycrystalline silicon film 19 is made to grow, and an emitter is formed through the ion-implantation of arsenic. The polycrystalline silicon film 19 is selectively etched, so that a collector contact opening 20, a base contact opening 21, or the like are provided.
JP63128845A 1987-05-29 1988-05-25 Bipolar transistor and manufacturing method thereof Expired - Fee Related JP2540912B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-137249 1987-05-29
JP13724987 1987-05-29

Publications (2)

Publication Number Publication Date
JPS6453454A true JPS6453454A (en) 1989-03-01
JP2540912B2 JP2540912B2 (en) 1996-10-09

Family

ID=15194252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63128845A Expired - Fee Related JP2540912B2 (en) 1987-05-29 1988-05-25 Bipolar transistor and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2540912B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233930A (en) * 1988-07-25 1990-02-05 Hitachi Ltd Semiconductor device
US5599723A (en) * 1993-12-22 1997-02-04 Nec Corporation Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance
US8716096B2 (en) 2011-12-13 2014-05-06 International Business Machines Corporation Self-aligned emitter-base in advanced BiCMOS technology

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0233930A (en) * 1988-07-25 1990-02-05 Hitachi Ltd Semiconductor device
US5599723A (en) * 1993-12-22 1997-02-04 Nec Corporation Method for manufacturing bipolar transistor having reduced base-collector parasitic capacitance
US8716096B2 (en) 2011-12-13 2014-05-06 International Business Machines Corporation Self-aligned emitter-base in advanced BiCMOS technology
US8916952B2 (en) 2011-12-13 2014-12-23 International Business Machines Corporation Self-aligned emitter-base in advanced BiCMOS technology

Also Published As

Publication number Publication date
JP2540912B2 (en) 1996-10-09

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees