JP2830053B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description of the Invention [Object of the Invention] (Industrial application field) The present invention relates to a method of manufacturing a semiconductor device having a low resistance buried region.

(Prior Art) As a conventional semiconductor device having a low resistance buried region,
For example, there is one as shown in FIG. 4 (edited by Minoru Nagata, “Ultra High-Speed Bipolar Device” Baifukan, p8, 60.11.15). In the figure, 1 is a p-type substrate, the p-type substrate 1 n ⁺ buried layer 2
Is formed by diffusion, and an n-type epitaxial layer 3 is formed thereon. The n-type epitaxial layer 3 has p
Ap ⁺ isolation region 4 is formed so as to reach the p-type substrate 1, and the n-type epitaxial layer 3 forms an n-type island region junction-separated from the p-type substrate 1.
In the n-type island region, a p-type base region 5, an n ⁺ emitter region 6 and an n ⁺ collector contact region 7 are formed using the n-type island region as a collector region, and these regions form a bipolar transistor. Have been.

The n ⁺ buried layer 2 reduces the collector resistance of the bipolar transistor.

(Problems to be Solved by the Invention) Conventionally, in order to form the n ⁺ buried layer 2 under the collector region, an epitaxial growth method has been essential for the process. For this reason, the number of processes increases, the substrate cost increases,
This has led to an increase in chip cost.

Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device which can form a low-resistance region in a semiconductor substrate without using an epitaxial growth method and can reduce a chip cost.

[Constitution of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides a first step of digging a plurality of parallel grooves at appropriate intervals by etching in a main surface of a semiconductor substrate. A second step of expanding the inside of the groove into a hollow shape by etching, a third step of forming a diffusion layer having a higher impurity concentration than the semiconductor substrate on an inner surface of the hollow portion, And a fourth step of embedding a polycrystalline or amorphous semiconductor into the semiconductor device.

(Operation) A plurality of parallel grooves are dug at appropriate intervals by etching in the main surface of the semiconductor substrate, and the inside of each groove is expanded into a hollow shape by etching. Next, a high impurity concentration diffusion layer serving as a low resistance region is formed on the inner surface of the hollow portion, and a polycrystalline or amorphous semiconductor is buried in the hollow portion. Thus, a low-resistance region can be formed in a semiconductor substrate without using an epitaxial growth method.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 and FIG. 2 are views showing one embodiment. This embodiment is applied to a method for manufacturing a bipolar transistor.

First, the configuration of a semiconductor device realized by the manufacturing method of this embodiment will be described with reference to FIG. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA of FIG.

In FIG. 1, reference numeral 101 denotes an n-type Si substrate as a semiconductor substrate. On the n-type Si substrate 101, an n-type island region 102 which is dielectrically separated by an insulating film 104 made of a SiO ₂ film is formed. An n ⁺ low resistance region 103 having a higher impurity concentration than that of the Si substrate 101 is formed in the intervening portion between the island region 102 and the insulating film 104. n
⁺ Low-resistance region 103 reaches the surface of Si substrate 101. n
The n-type island region 102 has a p-type base region 105, an n ⁺ emitter region 106, and an n ⁺
A collector contact region 107 is formed, and these regions form a bipolar transistor. Ten
8 is a buried region of polycrystalline Si or amorphous Si, and 109 is a surface insulating film.

The n ⁺ low resistance region 103 reduces the collector resistance of the bipolar transistor.

Next, a method for manufacturing the above-described semiconductor device will be described with reference to FIG. In the following description, (a) to
Each item symbol in (d) corresponds to each of (a) to (d) in FIG.

(A) For example, a {100} plane n-type Si substrate 101 is used, and an island region on the main surface is masked with a multilayer insulating film of SiO ₂ —Si ₃ N ₄ —SiO ₂ , and reactive ion etching is performed. Dig a plurality of parallel grooves 201.

(B) The inner surface of the groove 201 is etched using an alkaline anisotropic etchant such as hydrazine or ethylenediamine. When the inner surfaces of the exposed grooves 201 of the {110} and {100} surfaces are etched with an alkaline anisotropic etchant, the {110} and {100} surfaces have a significantly higher etch rate than the {111} surfaces. Therefore, etching stops when the {111} plane is exposed, and a hollow 2 having a diamond-shaped cross section
02 is formed.

(C) An n-type impurity is deposited at a high concentration on the inner surface of the cavity 202 by POCl ₃ or the like, and is driven in an oxidizing atmosphere to remove the n ⁺ low-resistance region 103 and the SiO ₂ film for dielectric isolation. An insulating film 104 is formed. Thus, the island region 102 is formed.

(D) Polycrystalline Si or amorphous Si is buried in the cavity 202 (an oxide film or an organic material such as PIQ may be used), the surface is flattened, a buried region 108 is formed, and the surface is further oxidized to form SiO 2.
₂ is formed.

Thereafter, a p-type base region 105, an n ⁺ emitter region 106, and an n ⁺ collector contact region are formed in the island region 102 according to a normal bipolar transistor forming process,
Further, a wiring and a surface protection process are performed.

As described above, according to the method of manufacturing the semiconductor device of this embodiment, the n ⁺ low resistance region 103 for reducing the collector resistance is formed at the bottom of the island region 102 separated from the dielectric without using the epitaxial growth method. You.

In the above-described embodiment, the island region 102 is dielectrically separated by the insulating film 104. However, the formation of the insulating film 104 is omitted, and the buried region 108 is made of p-type doped polycrystalline Si or the like. By setting the embedded region 108 to a low potential, pn junction isolation can be achieved.

Also, here, an example in which a groove is dug in the {100} plane as shown in FIG.
It goes without saying that a 0 ° plane substrate may be used.

Next, FIG. 3 shows another embodiment of the present invention.
This embodiment is applied to a method for manufacturing a MOSFET.

In this embodiment, ap ⁺ low resistance region 110 is formed below the island region 102, and a buried region 111 is made of p ^{+ -type} doped polycrystalline Si or amorphous Si. A MOSFET is formed in the island region 102 by the p ⁺ source region 112, the p ⁺ drain region 113, the gate electrode 114, and the like.

In this embodiment, the p ⁺ low resistance region 110 and the p ⁺ buried region 111
As a result, interaction with minority carriers due to other MOSFETs and the like is eliminated, and characteristics such as withstand voltage are improved.
Also in this embodiment, the p ⁺ low-resistance region 110 having the above-described function can be formed without using the epitaxial growth method.

In each of the above-described embodiments, anisotropic etching is used to form the cavity 202. Instead of this, isotropic etching may be used to form a cavity having a circular cross section.

[Effects of the Invention] As described above, according to the present invention, a plurality of parallel grooves are dug at appropriate intervals by etching in the main surface of a semiconductor substrate, and the inside of each groove is expanded into a hollow shape by etching. Then, a diffusion layer having a higher impurity concentration than the semiconductor substrate is formed on the inner surface of the hollow portion, and a polycrystalline or amorphous semiconductor is buried in the hollow portion. For example, a low-resistance region such as for reducing collector resistance can be formed in a semiconductor substrate, so that there is an advantage that a substrate cost can be reduced and a chip cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a view showing a semiconductor device manufactured by one embodiment of a method of manufacturing a semiconductor device according to the present invention. FIG. 2 is a process chart showing a method of manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 3 is a longitudinal sectional view showing a semiconductor device manufactured according to another embodiment of the present invention, and FIG. 4 is a longitudinal sectional view showing a conventional semiconductor device. 101: n-type Si substrate (semiconductor substrate), 102: island region, 103, 110: low resistance region (diffusion layer with a higher impurity concentration than the semiconductor substrate), 108, 111: embedded polycrystalline or amorphous semiconductor Area.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 27/08 331 H01L 29/78 301R 29/73 621 29/78 29/786

Claims (1)

(57) [Claims] A first step of digging a plurality of parallel grooves at appropriate intervals in a main surface of a semiconductor substrate by etching; a second step of enlarging the inside of the grooves into a hollow shape by etching; A third step of forming a diffusion layer having a higher impurity concentration than the semiconductor substrate on the inner surface of the hollow part, and a fourth step of embedding a polycrystalline or amorphous semiconductor in the hollow part. A method for manufacturing a semiconductor device, comprising: