KR20010064441A - Method of forming trench isolation layer in semiconductor device - Google Patents

Method of forming trench isolation layer in semiconductor device Download PDF

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Publication number
KR20010064441A
KR20010064441A KR1019990064638A KR19990064638A KR20010064441A KR 20010064441 A KR20010064441 A KR 20010064441A KR 1019990064638 A KR1019990064638 A KR 1019990064638A KR 19990064638 A KR19990064638 A KR 19990064638A KR 20010064441 A KR20010064441 A KR 20010064441A
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South Korea
Prior art keywords
trench
film
substrate
oxide film
device isolation
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KR1019990064638A
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Korean (ko)
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장훈
김광수
백성학
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990064638A priority Critical patent/KR20010064441A/en
Publication of KR20010064441A publication Critical patent/KR20010064441A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps

Abstract

PURPOSE: A forming method of device isolation film is provided to remarkably reduce the area of an element isolating film of the substrate surface by forming a trench-type element isolating film. CONSTITUTION: A pad oxide film and a nitride film are layered in sequence on a silicon substrate(100). Photoengraving and etching processes are performed using an element isolating mask to pattern the nitride film and the pad oxide film, and form trenches into a certain depth of the substrate. The substrate having the trench is wet etched to expand the trenches. A silicon epitaxial growth process is performed in the expanded trench areas to form epitaxial growth films in trench spaces. The pad oxide film and the nitride film are removed, and a gap-fill oxide films(114') are filled to produce air in the trenches. The gap-fill oxide films(114') are polished to expose the surface of the substrate to form trench-structured element isolating films.

Description

반도체장치의 트렌치 구조의 소자분리막 형성방법{Method of forming trench isolation layer in semiconductor device}Method of forming trench isolation layer in semiconductor device

본 발명은 반도체장치의 소자분리막 형성방법에 관한 것으로서, 특히 고집적 반도체장치에서 소자의 활성 영역과 비활성 영역을 정의하기 위한 트렌치 구조의 소자분리막의 면적을 줄여 칩 밀도(chip density)를 향상시킬 수 있는 반도체장치의 트렌치 구조의 소자분리막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation film of a semiconductor device. In particular, in a highly integrated semiconductor device, the chip density can be improved by reducing the area of the device isolation film having a trench structure for defining active and inactive regions of the device. A device isolation film formation method of a trench structure of a semiconductor device.

최근 반도체장치의 제조기술의 발달과 메모리소자의 응용분야가 확장되어 감에 따라 대용량의 메모리소자의 개발이 진척되고 있는데, 이러한 메모리소자의 대용량화는 각 세대마다 2배로 진행하는 미세공정기술을 기본으로 한 메모리셀 연구에 의해 추진되어 오고 있다. 특히 소자간을 분리하는 소자분리막의 축소는 메모리소자의 미세화 기술에 있어서 중요한 항목중의 하나로 대두되고 있다.Recently, as the development of semiconductor device manufacturing technology and the application of memory devices have been expanded, the development of large-capacity memory devices has been progressed. It has been promoted by a memory cell study. In particular, the reduction of the device isolation film that separates the devices has emerged as one of the important items in the technology of miniaturization of memory devices.

종래의 소자분리기술로는 반도체기판상에 두꺼운 산화막을 선택적으로 성장시켜 소자분리막을 형성하는 로커스(LOCal Oxidation of Silicon: 이하 LOCOS라 함) 기술이 최근까지 주종을 이루었다. 그러나, 상기 LOCOS 기술은 소자분리막의 측면확산 및 버즈비크(bird's beak)에 의해 소자분리영역의 폭을 감소시킬 수 없었다. 따라서, 소자설계치수가 서브미크론(submicron) 이하로 줄어드는 대용량의 메모리소자에 있어서는 LOCOS 기술의 적용이 불가능하기 때문에 새로운 소자분리 기술이 필요하게 되었다.Conventional device isolation technology has mainly been a LOCal Oxidation of Silicon (LOCOS) technology to selectively grow a thick oxide film on the semiconductor substrate to form a device isolation film. However, the LOCOS technique cannot reduce the width of the device isolation region due to side diffusion and bird's beak of the device isolation layer. Therefore, the LOCOS technology cannot be applied to a large-capacity memory device whose device design dimension is reduced to submicron or less, so a new device isolation technology is required.

이에 따라, 새로운 소자분리기술의 필요성과 식각(etching) 기술의 발달로 반도체기판에 폭 1Å이하, 깊이가 수십 내지 수백Å 정도의 트렌치를 형성하여 소자간을 전기적으로 분리할 수 있는 트렌치(trench) 구조의 소자분리 기술이 나오게 되었다. 이 트렌치를 이용한 소자분리기술은 종래의 LOCOS 기술에 비해 80%에 가까운 소자분리영역의 축소가 가능해졌다.As a result, a trench capable of electrically separating devices by forming trenches having a width of about 1Å or less and a depth of several tens to hundreds of Å on a semiconductor substrate due to the necessity of a new device isolation technology and the development of etching technology. Device isolation technology has emerged. The device isolation technology using this trench can reduce the device isolation region by nearly 80% compared to the conventional LOCOS technology.

본 발명의 목적은 고집적 반도체장치에서 트렌치 구조의 소자분리막 면적을 크게 줄이기 위하여 기판에 트렌치를 형성하고 습식 식각 공정을 실시하여 트렌치를 확장시킨 후에 실리콘 애피택셜성장(silicon epitaxial growth)을 실시하여 트렌치에 애피택셜막을 형성하고 트렌치에 갭필산화막을 매립하고 이를 연마해서 트렌치 구조의 소자분리막을 형성함으로써 기판 표면의 소자분리막 면적을 크게 줄일 수 있는 반도체장치의 트렌치 구조의 소자분리막 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to form a trench in a substrate in order to greatly reduce the area of a device isolation film of a trench structure in a highly integrated semiconductor device, and to perform a wet etching process to expand the trench, followed by silicon epitaxial growth. The present invention provides a method of forming a device isolation film having a trench structure in a semiconductor device, which can reduce an area of a device isolation film on a substrate surface by forming an epitaxial film, embedding a gapfill oxide film in a trench, and polishing the device to form a device isolation film having a trench structure.

도 1a 내지 도 1g는 본 발명에 따른 반도체장치의 트렌치 구조의 소자분리막 형성방법을 설명하기 위한 공정 순서도,1A to 1G are process flowcharts illustrating a method of forming an isolation layer in a trench structure of a semiconductor device according to the present invention;

도 2a 및 도 2b는 각각 통상적인 트렌치 구조의 소자분리막과 본 발명에 따른 개선된 트렌치 구조의 소자분리막을 비교하기 위한 단면도들.2A and 2B are cross-sectional views for comparing the device isolation film of the conventional trench structure with the device isolation film of the improved trench structure according to the present invention, respectively.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

100 : 실리콘기판 102 : 패드 산화막100 silicon substrate 102 pad oxide film

104 : 질화막 106 : 트렌치104: nitride film 106: trench

108 : 등방성 식각공정에 의해 확장된 트렌치108: trench extended by isotropic etching process

110 : 실리콘 애피택셜 성장막 112 : 에어110: silicon epitaxial growth film 112: air

114 : 갭필산화막 116 : 포토레지스트114 gap gap oxide film 116 photoresist

A : 기판의 활성 영역 ISO : 기판의 비활성 영역A: active area of substrate ISO: inactive area of substrate

상기 목적을 달성하기 위해 본 발명은 반도체소자의 트렌치 구조의 소자분리막을 형성함에 있어서, 실리콘기판에 순차적으로 패드산화막 및 질화막을 적층하는 단계와, 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 질화막과 패드산화막을 패터닝한 후에 기판의 소정 깊이까지 트렌치를 형성하는 단계와, 트렌치가 형성된 기판을 습식 식각하여 트렌치를 확장시키는 단계와, 확장된 트렌치 영역에 실리콘 애피택셜 성장공정을 실시하여 트렌치 공간에 애피택셜 성장막을 형성하는 단계와, 패드산화막 및 질화막을 제거하고 트렌치내부에 에어가 생성되도록 갭필산화막을 매립하는 단계와, 갭필산화막을 기판 표면이 드러날때까지 연마하여 트렌치 구조의 소자분리막을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming a device isolation film having a trench structure of a semiconductor device, by sequentially depositing a pad oxide film and a nitride film on a silicon substrate, and performing a photo and etching process using a device isolation mask. And forming a trench to a predetermined depth of the substrate after patterning the pad oxide layer, expanding the trench by wet etching the substrate on which the trench is formed, and performing a silicon epitaxial growth process on the extended trench region to form a trench in the trench space. Forming an epitaxial growth film, removing the pad oxide film and the nitride film, embedding the gapfill oxide film so that air is generated in the trench, and polishing the gapfill oxide film until the surface of the substrate is exposed to form a device isolation film having a trench structure Steps.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1g는 본 발명에 따른 반도체장치의 트렌치 구조의 소자분리막 형성방법을 설명하기 위한 공정 순서도로서, 이를 참조하면 본 발명의 개선된 트렌치 구조의 소자분리막을 갖는 반도체소자 제조 공정은 다음과 같다.1A to 1G are flowcharts illustrating a method of forming a device isolation film of a trench structure in a semiconductor device according to the present invention. Referring to this, a semiconductor device manufacturing process having an improved device for isolation of a trench structure according to the present invention is as follows. same.

우선, 도 1a에 도시된 바와 같이, 반도체기판인 실리콘기판(100)에 순차적으로 30∼100Å정도의 패드산화막(102) 및 500∼2000Å두께의 질화막(104)을 적층한다. 그 위에 소자분리마스크용 감광막(도시하지 않음)을 도포한 후에 건식 식각 공정을 실시하여 질화막(104)과 패드산화막(102)을 패터닝하고, 패터닝된 막에 의해 노출된 기판(100) 내에 트렌치(106)를 형성한다. 이때, 트렌치(106) 식각 깊이는 적용 디바이스의 디자인 룰에 따라 차이가 있으나 약 2000∼4000Å정도로 한다.First, as shown in FIG. 1A, a pad oxide film 102 having a thickness of about 30 to 100 microseconds and a nitride film 104 having a thickness of 500 to 2000 microseconds are sequentially stacked on a silicon substrate 100 which is a semiconductor substrate. After the photoresist film (not shown) for device isolation mask is applied thereon, a dry etching process is performed to pattern the nitride film 104 and the pad oxide film 102 and to form trenches in the substrate 100 exposed by the patterned film. 106). At this time, the trench 106 etching depth is different depending on the design rules of the application device is about 2000 ~ 4000Å.

그 다음, 도 1b 및 도 1c에 도시된 바와 같이 트렌치(106)가 형성된 기판(100)을 습식 식각하여 트렌치를 확장(108)시킨다. 일반적으로 습식 식각 공정이 실리콘기판의 (111)방향으로 진행되기 때문에 실리콘기판 표면에서의 트렌치 입구는 크게 변화되지 않으면서 트렌치 내부가 크게 확장된다.Next, as shown in FIGS. 1B and 1C, the substrate 100 having the trench 106 is wet-etched to expand the trench 108. In general, since the wet etching process is performed in the (111) direction of the silicon substrate, the trench inlet on the surface of the silicon substrate is greatly expanded without greatly changing the trench inlet.

그리고, 확장된 트렌치 영역(108)에 실리콘 애피택셜 성장공정을 실시하여 확장된 트렌치(108) 공간에 애피택셜 성장막(110)을 형성한다. 이때, 애피택셜 성장막(110)은 이후 기판의 활성 영역을 증가시키기 위함이다. 그리고, 실리콘 애피택셜 성장 공정은 트렌치 입구 부분에서 애피택셜 성장막(110)이 붙지 않도록 각 소자의 디자인 룰을 고려하여 설계한다.In addition, a silicon epitaxial growth process is performed on the extended trench region 108 to form an epitaxial growth layer 110 in the extended trench 108 space. At this time, the epitaxial growth layer 110 is to increase the active region of the substrate after. In addition, the silicon epitaxial growth process is designed in consideration of the design rule of each device so that the epitaxial growth film 110 does not adhere to the trench inlet.

그리고, 인산 용액으로 질화막(104)을 제거한 후에 세정공정을 실시하여 패드 산화막(102)을 제거한다.After the nitride film 104 is removed with the phosphoric acid solution, a cleaning process is performed to remove the pad oxide film 102.

그 다음, 도 1d에 도시된 바와 같이, 고밀도 플라즈마(High Density Plasma)를 이용하여 상기 트렌치에 에어(air)(112)가 생성되도록 갭필산화막(114)을 매립한다. 이때, 갭필산화막(114) 증착시 트렌치 중앙에 비해 기판방향의 입구 부분이 좁으므로 먼저 막히게 된다. 이에 따라, 트렌치 내부의 매립된 갭필산화막(114)에는 에어가 발생하게 되어 절연 특성이 크게 향상된다. 즉, 에어는 유전상수(ε)가 1에 가깝기 때문이다.Next, as shown in FIG. 1D, the gapfill oxide film 114 is embedded to generate air 112 in the trench using a high density plasma. At this time, since the inlet portion in the direction of the substrate is narrower than the center of the trench when the gap fill oxide film 114 is deposited, it is first blocked. As a result, air is generated in the gapfill oxide film 114 embedded in the trench, thereby greatly improving insulation characteristics. In other words, the air has a dielectric constant? Close to one.

그 다음, 도 1e 및 도 1f에 도시된 바와 같이, 갭필산화막(114)을 기판 표면이 드러날때까지 연마하되, 갭필산화막(114) 위에 포토레지스트(116)를 형성하고 전면 식각(etch back)공정을 진행하여 갭필산화막(114)을 연마한다. 이로 인해, 트렌치 내부에는 연마된 갭필산화막(114')이 매립되어 트렌치 구조의 소자분리막을 형성한다.Next, as shown in FIGS. 1E and 1F, the gap fill oxide layer 114 is polished until the surface of the substrate is exposed, and the photoresist 116 is formed on the gap fill oxide layer 114 and an etch back process is performed. Then, the gap fill oxide film 114 is polished. As a result, the polished gap fill oxide film 114 ′ is embedded in the trench to form a device isolation film having a trench structure.

이후, 도 1g에 도시된 바와 같이, 본 발명의 제조 방법에 따라 개선된 트렌치 구조의 소자분리막을 형성한 후에, 기판의 활성 영역에 게이트산화막(131), 게이트전극(132), LDD 영역(134), 스페이서(136) 및 소오스/드레인 접합(138)을 순차적으로 형성하여 모스 트랜지스터(130)를 완성한다.Thereafter, as shown in FIG. 1G, after the device isolation film having the improved trench structure is formed according to the manufacturing method of the present invention, the gate oxide film 131, the gate electrode 132, and the LDD region 134 are formed in the active region of the substrate. ), The spacer 136 and the source / drain junction 138 are sequentially formed to complete the MOS transistor 130.

도 2a 및 도 2b는 각각 통상적인 트렌치 구조의 소자분리막과 본 발명에 따른 개선된 트렌치 구조의 소자분리막을 비교하기 위한 단면도들이다.2A and 2B are cross-sectional views for comparing the device isolation film of the conventional trench structure with the device isolation film of the improved trench structure according to the present invention, respectively.

도 2a를 참조하면, 종래 트렌치 구조의 소자분리막은 폭은 좁고 깊이는 긴 트렌치 구조를 갖고 기판(10)에서 소자가 형성되어 전기적으로 통전이 가능한 활성 영역(A)과 전기적으로 통전이 불가능한 비활성 영역(ISO)을 정의한다.Referring to FIG. 2A, the device isolation layer of the conventional trench structure has a narrow trench structure having a narrow width and a long depth, and an inactive region in which an element is formed in the substrate 10 and an electrically conductive region that is not electrically conductive is possible. (ISO) is defined.

이에 반하여, 도 2b를 참조하면 본 발명의 트렌치 구조의 소자분리막은 기판 표면의 트렌치 폭이 좁고 트렌치의 중간 위치에 해당하는 폭이 넓기 때문에 종래 소자분리막(도 2a)에 비해 기판에서 비활성 영역(즉, 소자분리영역)의 면적이 감소되고 활성 영역(A)의 면적이 증가된다. 그리고, 본 발명의 소자분리막은 트렌치 내부에 에어를 갖고 있기 때문에 소자의 전기 절연 특성이 향상된다.On the contrary, referring to FIG. 2B, the device isolation film of the trench structure of the present invention has a narrow trench width on the substrate surface and a wide width corresponding to an intermediate position of the trench, so that an inactive region (ie, , The area of the device isolation region is reduced and the area of the active region A is increased. In addition, since the device isolation film of the present invention has air in the trench, the electrical insulating properties of the device are improved.

상술한 바와 같이, 본 발명은 기판에 트렌치를 형성하고 습식 식각 공정을 실시하여 트렌치를 확장시킨 후에 실리콘 애피택셜성장을 실시하여 기판의 활성 영역을 증가시키기 위한 애피택셜막을 형성하고 트렌치에 갭필산화막을 매립/연마해서 트렌치 구조의 소자분리막을 형성한다.As described above, in the present invention, a trench is formed in the substrate, and a wet etching process is performed to extend the trench, followed by silicon epitaxial growth to form an epitaxial film for increasing the active region of the substrate, and forming a gap fill oxide in the trench. Buried / polished to form a device isolation film of a trench structure.

이로 인해, 본 발명의 트렌치 구조의 소자분리막은 기판 표면의 트렌치 폭이 좁고 트렌치의 중간 위치에 해당하는 폭이 넓기 때문에 기판에서 비활성 영역(즉, 소자분리영역)의 면적이 감소되고 활성 영역(A)의 면적이 증가되어 칩의 밀도를 높일 수 있다. 그리고, 본 발명의 소자분리막은 트렌치 내부에 에어를 갖고 있으며트렌치 중간 위치의 소자분리막이 넓기 때문에 소자의 전기 절연 특성이 개선된다.As a result, the device isolation film of the trench structure of the present invention has a narrow trench width on the substrate surface and a wide width corresponding to an intermediate position of the trench, thereby reducing the area of the inactive region (that is, the device isolation region) on the substrate and the active region (A). ) Area can be increased to increase the density of the chip. In addition, the device isolation film of the present invention has air in the trench, and the device isolation film in the intermediate position of the trench is wide, so that the electrical insulation property of the device is improved.

Claims (3)

반도체소자의 트렌치 구조의 소자분리막을 형성함에 있어서,In forming a device isolation film having a trench structure of a semiconductor device, 실리콘기판에 순차적으로 패드산화막 및 질화막을 적층하는 단계;Sequentially depositing a pad oxide film and a nitride film on a silicon substrate; 소자분리마스크를 이용한 사진 및 식각 공정을 진행하여 상기 질화막과 패드산화막을 패터닝한 후에 기판의 소정 깊이까지 트렌치를 형성하는 단계;Performing a photolithography and etching process using a device isolation mask to pattern the nitride film and the pad oxide film, and then forming a trench up to a predetermined depth of the substrate; 상기 트렌치가 형성된 기판을 습식 식각하여 트렌치를 확장시키는 단계;Wet etching the substrate on which the trench is formed to extend the trench; 상기 확장된 트렌치 영역에 실리콘 애피택셜 성장공정을 실시하여 트렌치 공간에 애피택셜 성장막을 형성하는 단계;Forming an epitaxial growth film in the trench space by performing a silicon epitaxial growth process on the extended trench region; 상기 패드산화막 및 질화막을 제거하고 상기 트렌치내부에 에어가 생성되도록 갭필산화막을 매립하는 단계; 및Removing the pad oxide film and the nitride film and burying a gap fill oxide film to generate air in the trench; And 상기 갭필산화막을 기판 표면이 드러날때까지 연마하여 트렌치 구조의 소자분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체장치의 트렌치 구조의 소자분리막 형성방법.And forming a device isolation film having a trench structure by polishing the gap fill oxide layer until the substrate surface is exposed. 제 1항에 있어서, 상기 갭필산화막은 고밀도 플라즈마 방식의 산화막인 것을 특징으로 하는 반도체장치의 트렌치 구조의 소자분리막 형성방법.2. The method of claim 1, wherein the gap fill oxide film is a high density plasma oxide film. 제 1항에 있어서, 상기 갭필산화막의 연마 공정은 갭필산화막 위에 포토레지스트를 형성하고 전면 식각공정을 진행하는 것을 특징으로 하는 반도체장치의 트렌치 구조의 소자분리막 형성방법.The method of claim 1, wherein the polishing process of the gap fill oxide film is performed by forming a photoresist on the gap fill oxide film and performing an entire surface etching process.
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