US20060216878A1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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US20060216878A1
US20060216878A1 US11/169,707 US16970705A US2006216878A1 US 20060216878 A1 US20060216878 A1 US 20060216878A1 US 16970705 A US16970705 A US 16970705A US 2006216878 A1 US2006216878 A1 US 2006216878A1
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epitaxial layer
film
forming
region
gate
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US11/169,707
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Sang Lee
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SK Hynix Inc
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SK Hynix Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, SANG DON
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1052Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10894Multistep manufacturing methods with simultaneous manufacture of periphery and memory cells
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/10882Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line
    • H01L27/10888Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making a data line with at least one step of making a bit line contact

Abstract

A method for fabricating a semiconductor device is provided, the method including forming a SiGe epitaxial layer pattern and a first Si epitaxial layer pattern on a semiconductor substrate, forming a second Si epitaxial layer on the entire surface, etching the second Si epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region, removing the SiGe epitaxial layer pattern through a sidewall of the trench to form a space under the first Si epitaxial layer, forming a gap-filling insulating film to at least fill up the space and the trench, forming a gate oxide film on the second Si epitaxial layer, and depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer in order to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer under a bit line contact and the semiconductor substrate, thereby improving a characteristic of a leakage current for a storage node junction.
  • 2. Description of the Related Art
  • FIG. 1 is a layout illustrating a conventional method for fabricating a semiconductor device, wherein reference numerals 1000 a, 1, 2 and 3 denote a cell region, an active region, a first gate region and a second gate region, respectively.
  • FIGS. 2 a through 2 f are cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2 a(i) through 2 f(i) are cross-sectional views taken along the line I-I′ in FIG. 1, and FIGS. 2 a(ii) through 2 f(ii) are cross-sectional views in a core/peripheral circuit region 1000 b.
  • Referring to FIG. 2 a, a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown), a first oxide film (not shown) and a first nitride film (not shown) is formed on a semiconductor substrate 10 having a cell region 1000 a and a core/peripheral circuit region 1000 b defined therein.
  • Next, a first photoresist film (not shown) is deposited on the entire surface of the first nitride film (not shown) in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Thereafter, the first photoresist film (not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the first gate region 2 of FIG. 1 and cover the entire core/peripheral circuit region 1000 b.
  • After that, the stacked structure is etched using the first photoresist film pattern as an etching mask to expose the semiconductor substrate 10 of the first gate region 2 and the entire core/peripheral circuit region 1000 b.
  • The first photoresist film pattern is then removed.
  • Referring FIG. 2 b, a first nitride film pattern 19 and a first oxide film pattern 17 in the cell region 1000 a are removed via a wet etching method.
  • Next, a second Si expitaxial layer 25 is formed on the entire surface of the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Referring to FIG. 2 c, a second oxide film 30 and a second nitride film 35 are formed on the second Si epitaxial layer 25 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Next, a second photoresist film (not shown) is deposited on the entire surface of the second nitride film 35. The second photoresist film is then exposed and developed to form a second photoresist film pattern (not shown) defining the active region 1 of FIG. 1 in the cell region 1000 a, and also an active region in the core/peripheral circuit region 1000 b.
  • Thereafter, the second nitride film 35, the second oxide film 30, the second Si epitaxial layer 25, the first Si epitaxial layer pattern 15, the SiGe epitaxial layer pattern 13 and a predetermined thickness of the semiconductor substrate 10 are etched using the second photoresist film pattern as an etching mask to form a trench 40 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • After that, the second photoresist film pattern (not shown) is removed. The SiGe epitaxial layer pattern 13 is then etched through a sidewall of the trench 40 via a wet etching method to form a space 27 under the first Si epitaxial layer pattern 15.
  • Referring to FIG. 2 d, a gap-filling insulating film 45 is formed on the entire surface to fill up the space 27 and the trench 40 in the cell region 1000 a and to fill up the trench 40 in the core/peripheral circuit region 1000 b.
  • Next, the gap-filling insulating film 45 is polished until the second nitride film 35 is exposed. The gap-filling insulating film 45 serves as a device isolation film.
  • Thereafter, a predetermined thickness of the gap-filling insulating film 45 in the trench 40 is etched. The second nitride film 35 is then removed via a wet etching method.
  • After that, a well implant process and a channel implant process are performed so as to adjust impurity concentrations in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Referring to FIG. 2 e, the second oxide film 30 in the cell region 1000 a and the core/peripheral circuit region 1000 b is removed via a wet etching method to expose the second Si epitaxial layer 25. A gate oxide film 50 is then formed on the exposed second Si epitaxial layer 25.
  • Next, gate conductive layers 60 and 70, and a hard mask insulating film 80 are formed on the gate oxide film 50 and the gap-filling insulating film 45 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Referring to FIG. 2 f, a third photoresist film (not shown) is deposited on the hard mask insulating film 80 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • Thereafter, the third photoresist film (not shown) is exposed and developed to form a third photoresist film pattern defining the second gate region 3 of FIG. 1 and a gate region (not shown) in the core/peripheral circuit region 1000 b. Specifically, the third photoresist film pattern exposes a bit line contact region and storage node contact regions in the cell region 1000 a and covers a region where a gate is to be formed in the core/peripheral circuit region 1000 b.
  • Next, the hard mask insulating film 80 and the gate conductive layers 70 and 60 are etched using the third photoresist film pattern as an etching mask to respectively form a gate 90 in the cell region 1000 a and the core/peripheral circuit region 1000 b.
  • However, in accordance with the above-described conventional method, the gate 90 of the active region is formed on a plane second Si epitaxial layer. As a result, a gate channel length is decreased as a design rule of the semiconductor device is reduced.
  • Moreover, an oxide film is formed at the interface of the Si epitaxial layer under a storage node contact and the semiconductor substrate. Accordingly, the leakage current for a storage node junction is highly depended upon an interface characteristic between the Si epitaxial layer and an oxide film.
  • In addition, the SiGe epitaxial layer under the storage node contact is removed for forming a device isolation film. As a result, Ge in the SiGe epitaxial layer is diffused into the first Si epitaxial layer, the second Si epitaxial layer and the semiconductor substrate due to heat treatment processes prior to the formation of the device isolation film. Accordingly, there is a problem such as increase in the leakage current for the storage node junction.
  • SUMMARY OF THE INVENTION
  • It is an object of the present invention to provide a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer under a bit line contact and the semiconductor substrate, thereby improving a characteristic of a leakage current for a storage node junction.
  • In order to achieve the object of the present invention, there is provided a method for fabricating a semiconductor device comprising the steps:
  • (a) forming a SiGe epitaxial layer, a first Si epitaxial layer and an insulating film on a semiconductor substrate, (b) etching a predetermined region of the insulating film, the first Si epitaxial layer and the SiGe epitaxial layer to expose the semiconductor substrate, wherein the predetermined region includes a storage node contact region and a portion of a gate region adjacent thereto, (c) removing the insulating film, (d) forming a second Si epitaxial layer on the entire surface including the exposed semiconductor substrate, (e) etching the second Si epitaxial layer, the first Si epitaxial layer, the SiGe epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region, (f) removing the SiGe epitaxial layer through a sidewall of the trench to form a space under the first Si epitaxial layer, (g) forming a gap-filling insulating film to at least fill up the space and the trench, (h) forming a gate oxide film on the second Si epitaxial layer, and (i) depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a layout illustrating a conventional method for fabricating a semiconductor device.
  • FIGS. 2 a through 2 f are cross-sectional views illustrating a conventional method for fabricating a semiconductor device.
  • FIG. 3 is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention.
  • FIGS. 4 a through 4 f and FIG. 5 are cross-sectional views illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS
  • Reference will now be made in detail to exemplary embodiments of the present invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
  • FIG. 3 is a layout illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention, wherein reference numerals 2000 a, 101, 102 and 103 denote a cell region, an active region, a contact region and a gate region, respectively.
  • FIGS. 4 a through 4 f illustrate a method for fabricating a semiconductor device according to a preferred embodiment of the present invention, wherein FIGS. 4 a(i) through 4 f(i) are cross-sectional views taken along the line II-II′ of FIG. 3, and FIGS. 4 a(ii) through 4 f(ii) are cross-sectional views in a core/peripheral circuit region 2000 b.
  • Referring to FIG. 4 a, a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown) and an insulating film (not shown) is formed on a semiconductor substrate 110 having a cell region 2000 a and a core/peripheral circuit region 2000 b defined therein. Preferably, the insulating film comprises an oxide film or a stacked structure of an oxide film and a nitride film.
  • Next, a first photoresist film (not shown) is deposited on the entire surface of the insulating film in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • Thereafter, the first photoresist film (not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the contact region 102 of FIG. 3 and cover the entire core/peripheral circuit region 2000 b. The contact region 102 includes a storage node contact region and a portion of the gate region 103 adjacent thereto. Preferably, the portion of the gate region 103 has a line width of M ranging from ⅓F to F, where F is a gate line width.
  • After that, the stacked structure is etched using the first photoresist film pattern as an etching mask to expose the semiconductor substrate 110 of the contact region 102 and the entire core/peripheral circuit region 2000 b.
  • The first photoresist film pattern is then removed.
  • Referring to FIG. 4 b, an insulating film pattern 120 in the cell region 2000 a is removed. Preferably, the removal process for the insulating film pattern 120 is performed via a wet etching method.
  • Next, a second Si epitaxial layer 125 is formed on the entire surface of the cell region 2000 a and the core/peripheral circuit region 2000 b. Preferably, a thickness of the second Si epitaxial layer 125 ranges from 10 nm to 100 nm.
  • The second epitaxial layer 125 in the cell region 2000 a may have a step difference due to the first Si epitaxial layer pattern 115 and the SiGe epitaxial layer pattern 113.
  • Referring to FIG. 4 c, a second oxide film 130 and a second nitride film 135 are formed on the second Si epitaxial layer 125 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • Next, a second photoresist film (not shown) is deposited on the entire surface of the second nitride film 135. The photoresist film is then exposed and developed to form a second photoresist film pattern (not shown) defining the active region 101 of FIG. 3 in the cell region 2000 a and also an active region in the core/peripheral circuit region 2000 b.
  • Thereafter, the second nitride film 135, the second oxide film 130, the second Si epitaxial layer 125, the first Si epitaxial layer pattern 115, the SiGe epitaxial layer pattern 113 and a predetermined thickness of the semiconductor substrate 110 are etched using the second photoresist film pattern as an etching mask to form a trench 140 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • After that, the second photoresist film pattern (not shown) is removed. The SiGe epitaxial layer pattern 113 is then etched through a sidewall of the trench 140 to form a space 127 under the first Si epitaxial layer pattern 115.
  • FIG. 5 is a cross-sectional view taken along the line III-III′ of FIG. 3 illustrating the structure of FIG. 4 c(i) including the space 127 having a undercut structure.
  • Preferably, the removal process for the SiGe epitaxial layer pattern 113 is preformed via a wet etching method utilizing a mixed etchant containing HF, H2O2 and CH3CHOOH, a plasma etching method utilizing a mixed gas containing (CF3 or CH2F2), N2 and O2, or combinations thereof. Moreover, a volume ratio of HF, H2O2 and CH3COOH in the mixed etchant is preferably 1:2:3.
  • Referring to FIG. 4 d, a gap-filling insulating film 145 is formed on the entire surface to at least fill up the space 127 and the trench 140 in the cell region 2000 a and to fill up the trench 140 in the core/peripheral circuit region 2000 b.
  • Preferably, the formation process of the gap-filling insulating film 145 may include forming a thermal oxide film filling up the space 127 and forming an oxide film for a device isolation film filling up the trench 140. A nitride film may be further formed at an interface of the thermal oxide film and the oxide film for the device isolation film.
  • Moreover, the formation process of the gap-filling insulating film 145 may include forming a thermal oxide film to fill up a portion of the space 127, forming a nitride film to fill up the remaining portion of the space 127, and forming an oxide film for the device isolation film to fill up the trench 140.
  • Next, the gap-filling insulating film 145 is polished until the second nitride film 135 is exposed. The gap-filling insulating film 145 in the trench 140 serves as a device isolation film.
  • Thereafter, a predetermined thickness of the gap-filling insulating film 145 in the trench 140 is etched. The second nitride film 135 is then removed. Preferably, the etching process for the gap-fill insulating film 145 is performed via a wet etching method. The removal process for the second nitride film 135 is preferably preformed via a wet etching method.
  • After that, well implant processes and channel implant processes are performed so as to respectively adjust impurity concentrations in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • Referring to FIG. 4 e, the second oxide film 130 in the cell region 2000 a and the core/peripheral circuit region 2000 b is removed to expose the second Si epitaxial layer 125. A gate oxide film 150 is then formed on the exposed second Si epitaxial layer 125. Preferably, the removal process for the second oxide film 130 is performed via a wet etching method.
  • Next, a stacked structure of a gate conductive layer 175 and a hard mask layer 180 is formed on the gate oxide film 150 and the gap-filling insulating film 145 in the cell region 2000 a and the core/peripheral circuit region 2000 b. Preferably, the gate conductive layer 175 comprises a lower conductive layer 160 and an upper conductive layer 170.
  • Referring to FIG. 4 f, a third photoresist film (not shown) is deposited on the hard mask layer 180 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • Thereafter, the third photoresist film (not shown) is exposed and developed to form a third photoresist film pattern defining the gate region 103 of FIG. 3 and a gate region (not shown) in the core/peripheral circuit region 2000 b. Specifically, the third photoresist film pattern exposes a bit line contact region and storage node contact regions in the cell region 2000 a and covers a region where a gate is to be formed in the core/peripheral circuit region 2000 b.
  • Next, the stacked structure is patterned using the third photoresist film pattern as an etching mask to respectively form a gate 190 in the cell region 2000 a and the core/peripheral circuit region 2000 b.
  • In addition, subsequent processes such as an ion-implant process for forming source/drain regions in the active regions, a process for forming a spacer on a sidewall of the gate 190, a process for forming a landing plug, a process for forming a bit line contact and a bit line, a process for forming a capacitor and a process for forming an interconnect may be done.
  • As described above, the method for fabricating a semiconductor device in accordance with the present invention provides exposing the contact region including the storage node contact region and a portion of the gate region adjacent thereto and only forming an oxide film at the interface of the Si epitaxial layer under both a bit line contact and the semiconductor substrate. Accordingly, capacitance for a bit line contact and a short-channel effect of a cell transistor are improved.
  • As shown in FIG. 4 f, the gate 190 in the cell region 2000 a is formed on a structure having a step difference instead of over a plane structure to increase an effective length of the gate channel, and the storage node contact is formed on the Si epitaxial layer without the oxide film to minimize the leakage current of the storage node junction. Accordingly, a refresh characteristic of a DRAM can be improved.
  • The foregoing description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated.

Claims (12)

1. A method for fabricating a semiconductor device, comprising the steps of:
(a) forming a SiGe epitaxial layer, a first Si epitaxial layer and an insulating film on a semiconductor substrate;
(b) etching a predetermined region of the insulating film, the first Si epitaxial layer and the SiGe epitaxial layer to expose the semiconductor substrate, wherein the predetermined region includes a storage node contact region and a portion of a gate region adjacent thereto;
(c) removing the insulating film;
(d) forming a second Si epitaxial layer on the entire surface including the exposed semiconductor substrate;
(e) etching the second Si epitaxial layer, the first Si epitaxial layer, the SiGe epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region;
(f) removing the SiGe epitaxial layer through a sidewall of the trench to form a space under the first Si epitaxial layer;
(g) forming a gap-filling insulating film to at least fill up the space and the trench;
(h) forming a gate oxide film on the second Si epitaxial layer; and
(i) depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.
2. The method according to claim 1, wherein the step (b) comprises:
forming a photoresist film on the entire surface of the semiconductor substrate;
forming a photoresist film pattern exposing the predetermined region by exposing and developing the photoresist film, wherein the portion of the gate region of the predetermined region has a line width of M; and
etching the insulating film, the Si epitaxial layer and the SiGe epitaxial layer using the photoresist film pattern as an etching mask.
3. The method according to claim 2, wherein the M ranges from ⅓F to F, wherein F is a gate line width.
4. The method according to claim 1, wherein the insulating film comprises an oxide film.
5. The method according to claim 1, wherein the insulating film comprises a stacked structure of an oxide film and a nitride film.
6. The method according to claim 1, wherein the removal process for the insulating film in the step (e) is performed via a wet etching method.
7. The method according to claim 1, wherein a thickness of the second Si epitaxial layer ranges from 10 to 100 nm.
8. The method according to claim 1, wherein the removal process for the SiGe epitaxial layer in the step (f) is performed via one method selected from the group consisting of a wet etching method utilizing a mixed etchant containing HF, H2O2 and CH3COOH, a plasma etching method utilizing a mixed gas containing (CF4 or CH2F2), N2 and O2, and combinations thereof.
9. The method according to claim 8, wherein a volume ratio of HF, H2O2 and CH3COOH in the mixed etchant is 1:2:3.
10. The method according to claim 1, wherein the step (g) comprises:
forming a thermal oxide film filling up the space; and
forming an oxide film for a device isolation film to fill up the trench.
11. The method according to claim 10, further comprising
forming a nitride film at the interface of the thermal oxide film and the oxide film for the device isolation film.
12. The method according to claim 1, wherein the step (g) comprises:
forming a thermal oxide film to fill a portion of the space;
forming a nitride film to fill up a remaining portion of the space; and
forming an oxide film for the device isolation film to fill up the trench.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150126040A1 (en) * 2013-11-04 2015-05-07 Applied Materials, Inc. Silicon germanium processing
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9449850B2 (en) 2013-03-15 2016-09-20 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100610465B1 (en) * 2005-03-25 2006-08-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR20130037551A (en) * 2011-10-06 2013-04-16 삼성전자주식회사 Methods for forming semiconductor devices and semiconductor devices formed of the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166084A (en) * 1991-09-03 1992-11-24 Motorola, Inc. Process for fabricating a silicon on insulator field effect transistor
US20050250294A1 (en) * 2003-02-28 2005-11-10 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089428A (en) * 1989-12-27 1992-02-18 Texas Instruments Incorporated Method for forming a germanium layer and a heterojunction bipolar transistor
US5268324A (en) * 1992-05-27 1993-12-07 International Business Machines Corporation Modified silicon CMOS process having selectively deposited Si/SiGe FETS
US5422305A (en) * 1993-10-29 1995-06-06 Texas Instruments Incorporated Method of forming implanted silicon resonant tunneling barriers
US5466949A (en) * 1994-08-04 1995-11-14 Texas Instruments Incorporated Silicon oxide germanium resonant tunneling
JPH1050820A (en) 1996-08-01 1998-02-20 Nittetsu Semiconductor Kk Semiconductor device and its manufacture
KR100320729B1 (en) 1999-06-18 2002-01-19 밍-퉁 센 Semiconductor chip module and method for manufacturing the same
DE60045126D1 (en) * 1999-06-25 2010-12-02 Massachusetts Inst Technology Oxidation of a germanium layer on a silicon layer deposited
US6429061B1 (en) 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
KR100610465B1 (en) * 2005-03-25 2006-08-01 주식회사 하이닉스반도체 Method for fabricating semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5166084A (en) * 1991-09-03 1992-11-24 Motorola, Inc. Process for fabricating a silicon on insulator field effect transistor
US20050250294A1 (en) * 2003-02-28 2005-11-10 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US10062578B2 (en) 2011-03-14 2018-08-28 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US10062587B2 (en) 2012-07-18 2018-08-28 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US10032606B2 (en) 2012-08-02 2018-07-24 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US10354843B2 (en) 2012-09-21 2019-07-16 Applied Materials, Inc. Chemical control features in wafer process equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9704723B2 (en) 2013-03-15 2017-07-11 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9659792B2 (en) 2013-03-15 2017-05-23 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9449850B2 (en) 2013-03-15 2016-09-20 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US20150126040A1 (en) * 2013-11-04 2015-05-07 Applied Materials, Inc. Silicon germanium processing
US9236265B2 (en) * 2013-11-04 2016-01-12 Applied Materials, Inc. Silicon germanium processing
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9837249B2 (en) 2014-03-20 2017-12-05 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9564296B2 (en) 2014-03-20 2017-02-07 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9269590B2 (en) 2014-04-07 2016-02-23 Applied Materials, Inc. Spacer formation
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9773695B2 (en) 2014-07-31 2017-09-26 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9478434B2 (en) 2014-09-24 2016-10-25 Applied Materials, Inc. Chlorine-based hardmask removal
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9837284B2 (en) 2014-09-25 2017-12-05 Applied Materials, Inc. Oxide etch selectivity enhancement
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9299583B1 (en) 2014-12-05 2016-03-29 Applied Materials, Inc. Aluminum oxide selective etch
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US10147620B2 (en) 2015-08-06 2018-12-04 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10224180B2 (en) 2016-10-04 2019-03-05 Applied Materials, Inc. Chamber with flow-through source
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10319603B2 (en) 2016-10-07 2019-06-11 Applied Materials, Inc. Selective SiN lateral recess
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10186428B2 (en) 2016-11-11 2019-01-22 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10325923B2 (en) 2017-02-08 2019-06-18 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch

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