JPH0233930A - Semiconductor device - Google Patents

Abstract

PURPOSE:To optimize the resistance of a base region and the junction capacity between a collector and a base in order to improve operation speed thereof by partially forming a graft base on the circumference of an intresic base region and an emitter region. CONSTITUTION:A graft base 2a is partially formed on the circumference of a base region 2 and an emitter region 3. In other words, a semiconductor region which becomes the base region 2 and the emitter region 3 of an SEPT transistor in an epitaxial layer 1 is formed. Here the base region 2 and the emitter region 3 are constituted so that the cross-sectional view thereof shows rectangle, the graft base 2a in which a part of the base region 2 is constituted is formed at two positions of a long side and a polysilicon base drawing electrode 4 is constituted so that it is brought into contact therewith in a region in which the graft base 2a is formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a technique that is particularly effective when applied to the formation of semiconductor integrated circuits. Regarding technology.

[Prior Art] Generally, self-aligned semiconductor devices such as SST and 5EPT devices have a structure in which a graft base is disposed over the entire region around an intrinsic base region and an emitter region.

Incidentally, the operating speed of the semiconductor device as described above depends on the base resistance and the collector-base junction capacitance. The latter collector-base junction capacitance is represented by the sum of the intrinsic base capacitance, the graft base capacitance, and the MIS capacitance.

Of these, if we look only at the base resistance, the lower it is, the more it will contribute to speeding up the semiconductor device.If we adopt a structure in which the graft base is disposed over the entire region around the intrinsic base region and emitter region as described above, Since the base resistance is lowered as a whole, the speed of the semiconductor device can be increased.

[Problems to be Solved by the Invention] However, on the other hand, when a graft base is provided around the intrinsic base region and the emitter region, the spread of the depletion layer becomes smaller, so that the collector-base junction capacitance increases.

This tendency is particularly noticeable when the graft base is disposed over the entire region around the intrinsic base region and the emitter region as described above.

Although it depends on the shape and depth of the emitter region and the base region of the semiconductor device, carelessly providing the graft base may actually reduce the operating speed of the semiconductor device.

The present invention has been made in view of this point, and an object of the present invention is to provide a semiconductor device having a structure capable of increasing speed.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in Hyohara are summarized as follows.

That is, in the semiconductor device according to the present invention, a graft base is partially formed around the intrinsic base region and the emitter region.

[Operation] According to the above-mentioned means, since the graft base is partially formed around the intrinsic base region and the emitter region, the resistance of the base region and the collector-base junction capacitance can be reduced to improve the operating speed. By optimizing the semiconductor device in a way that contributes to the performance, the speed of the semiconductor device can be increased.

[Example] Hereinafter, a semiconductor device according to the present invention will be described based on the drawings.

FIG. 1 is a plan view of the emitter region and base region of the 5EPT transistor of this example, and FIG.
B) is a vertical sectional view taken along lines AA and BB in FIG. 1.

In FIGS. 2(A) and 2(B), reference numeral 1 represents an N- type epitaxial layer formed on a P-type silicon substrate having an N+-type buried layer, and this epitaxial layer 1 includes 5EPT transistors. Semiconductor regions serving as a base region 2 and an emitter region 3 are formed. Here, the base region 2 and the emitter region 3 are configured so that their cross-sectional view has a rectangular shape as shown in the first part, and the base region 2
Graft bases 2a constituting a part of the graft base 2a are formed at two locations on the long side, and the polysilicon base extraction electrode 4 is contacted in the region where the graft bases 2a are formed. In other words, the 5EPT transistor of this embodiment has a structure in which the graft base on the shorter side of the graft base, which was conventionally formed over the entire area around the emitter region, is omitted. In addition,
In FIGS. 2A and 2B, reference numeral 5 represents a polysilicon emitter lead electrode that contacts the emitter region 2. In FIGS.

Next, an example of a method for manufacturing the above semiconductor device will be described.

First, N+ is partially deposited on a semiconductor substrate made of P-type silicon.
A buried layer is formed, an N-type epitaxial layer N1 is grown on it by vapor phase growth, and an oxide film (Si
An O2 film) 6 and a nitride film (Si, N,) are formed. Thereafter, using the oxide film 6 and the nitride film as a mask, the main surface of the substrate is slightly shaved and thermal oxidation is performed to form a relatively thick field oxidation side for isolation between elements, and then the nitride film is removed.

Then, a collector lift consisting of an N+ type diffusion layer is formed, followed by the active region of the 5EPT transistor.

Below, Figures 3 (A) to (E) and Figures 4 (A, ) to
A method for manufacturing an active region of a 5EPT transistor will be explained using FIG. Here, FIGS. 3(A) to 3(E) are cross-sectional views at each step along the line AA' in FIG. 1, and FIG.
) to (E) represent cross-sectional views at each step along line BB' in FIG.

A nitride film 7 is deposited on the entire surface of the oxide film 6, a non-doped polysilicon 8, an oxide film 9 and a nitride film 10 are sequentially formed on the surface, and a photoresist is applied.
An emitter is placed on the part that will become the element area by optical engraving.
A photoresist coating 11 having base information is formed. Next, using this photoresist film 11 as a mask, the nitride film 10 immediately below it is selectively etched, and boron (B) ions are implanted using the photoresist film 11 as a mask. The state that has been completed up to this point is shown in Figure 3 (A
), as shown in FIG. 4(A).

After that, the photoresist film 11 is removed and annealing is performed. As a result, the outer part of the mask becomes boron-doped polysilicon 8a (the number 8a is used to distinguish it from the non-doped polysilicon 8), while the lower part of the mask becomes The non-doped polysilicon 8 remains as it is.

Next, the surface is coated with a photoresist film 12 such that only the oxide film 9 on the area where the graft base is to be formed is exposed.
(FIG. 5), and using this photoresist film 12 and the nitride film 10 as a mask, the oxide film 9 underneath is etched. At this time, only the oxide film 9 on the region where the graft base is to be formed will be etched, but in this case, side etching of the oxide film 9 is performed as shown in FIG. 4(B).

As shown in FIG. 6, the photoresist coating 12 may be a photoresist coating that covers only the short side of the region where the base is to be formed.

Then, the photoresist coating 12 and nitride film 10 that served as a mask are removed, and the remaining oxide film 9 located below them is used as a mask to etch the non-doped polysilicon 8 with radish or the like. A part of the nitride film 7 under the non-doped polysilicon 8 is exposed, resulting in the state shown in FIGS. 3(C) and 4(C).6Then, the oxide film 9 used as a mask is removed. After that, the exposed nitride film 7 is etched using the non-doped polysilicon 8 and the boron-doped polysilicon 8a as a mask, and then the non-doped polysilicon 8 used as a mask is etched.
is removed, resulting in the states shown in FIGS. 3(D) and 4(D).

In this state, boron ions are implanted into the region where the connecting base is to be formed and the region where the graft base is to be formed.

Next, non-doped polysilicon 13 is deposited and annealed. Then, the boron implanted into the boron-doped polysilicon 8a and the region where the graft penis is to be formed diffuses (oil drains), and the non-doped polysilicon changes to boron-doped polysilicon 13a except the region where the emitter hole is to be formed. Next, the non-doped polysilicon is etched using hydrazine or the like, and then the boron-doped polysilicon 8a, 13a, which will become the polysilicon base extraction electrode 4 (FIGS. 2(A) and 2(B)), is etched.

After that, boron-doped polysilicon 13 is formed by thermal oxidation.
After oxidizing the surface of a to form an oxide film 14, using this as a mask, nitride film 7 is formed inside the area where the emitter hole is to be opened.
and oxide film 6 are removed by dry etching.

According to the 5EPT transistor configured as described above, the following effects can be obtained.

That is, according to the above 5EPT transistor, since the graft base 2a is partially formed around the intrinsic base region and the emitter region 3, the base resistance and the collector-base junction capacitance are reduced in order to improve the operation speed. Due to the optimization effect, the speed of the semiconductor device can be increased.

In addition, since the manufacturing process only requires the step of applying the photoresist coating 12 as described above, there is no significant reduction in throughput.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

Furthermore, in the above explanation, the invention made by the present inventor was mainly applied to the 5EPT transistor, which is the field of application that formed the background of the invention, but S'ST,
5ICOS and other semiconductor devices. In short,
Any semiconductor device may be used as long as it has a graft base formed around an intrinsic base region and an emitter region.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In the semiconductor device according to the present invention, a graft base is partially formed around the intrinsic base region and the emitter region, and the resistance of the base region and the collector-base junction capacitance are optimized to improve the operating speed. As a result, the operating speed of the semiconductor device can be improved, in other words, the speed of the semiconductor device can be increased.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the base region and emitter region of a 5EPT transistor which is an embodiment of the present invention, and FIG.
2 is a vertical cross-sectional view of the 5EPT transistor shown in FIG.
A) is a vertical cross-sectional view taken along the line A-A' in Figure 1, and Figure 2 (B
) is a vertical cross-sectional view taken along the line BB' in Figure 1, and Figures 3 (A) to (E) are longitudinal cross-sectional views taken along the line AA' in Figure 1 to explain the manufacturing method of the 5EPT transistor in Figure 1. 4 (A) to (E) are longitudinal sectional views at each step along line BB' for explaining the manufacturing method of the 5EPT transistor shown in FIG. 1; 6 is a plan view showing the relationship between the photoresist film used to form the graft base and the base region, and FIG. 6 shows the relationship between the base region and another photoresist film used to form the graft base. FIG. 1...Epitaxial layer, 2...Base region,
2a...Graft base, 3...Emitter region. Figure 1 Figure 3 (A) 3' Figure 2 (E) Figure (A) (E) Figure 5

Claims (1)

[Claims] 1. A buried layer having a conductivity type different from that of the semiconductor substrate is formed on the main surface of the semiconductor substrate, and an epitaxial layer having the same conductivity type as the buried layer is formed thereon, and In a semiconductor device in which a diffusion layer serving as a base region and an emitter region of a bipolar transistor is formed in this epitaxial layer, and a graft base region constituting a part of the base region is further formed around the emitter region, the graft base region is formed partially around the intrinsic base region and the emitter region. 2. The semiconductor device according to claim 1, wherein the base region including the graft base has a rectangular cross section, and the graft base is formed at two locations on the long sides of the base region.