KR19980028510A - Device Separation Method of Semiconductor Devices - Google Patents
Device Separation Method of Semiconductor Devices Download PDFInfo
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- KR19980028510A KR19980028510A KR1019960047572A KR19960047572A KR19980028510A KR 19980028510 A KR19980028510 A KR 19980028510A KR 1019960047572 A KR1019960047572 A KR 1019960047572A KR 19960047572 A KR19960047572 A KR 19960047572A KR 19980028510 A KR19980028510 A KR 19980028510A
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- gate electrode
- device isolation
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000000926 separation method Methods 0.000 title description 5
- 238000002955 isolation Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000007772 electrode material Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims 3
- 238000009413 insulation Methods 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- 229920005591 polysilicon Polymers 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
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- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
본 발명은 표면 단차가 개선된 반도체 디바이스의 소자 분리 방법이 개시된다. 개시된 본 발명은, 종래의 로코스 기술에 따른 버즈 빅 및 표면 단차를 감소시키기 위한 것으로, 본 발명은 반도체 기판 상부에 게이트 산화막과 게이트 전극용 막을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 해당하는 게이트 전극용 막, 게이트 산화막 및 반도체 기판의 소정 깊이만큼을 식각하여 트랜치를 형성하는 단계; 반도체 기판의 결과물이 충분히 매립되도록 소자 분리막용 절연막을 형성하는 단계; 상기 소자 분리막용 절연막을 게이트 전극용 물질의 표면이 노출되도록 에치백하여 트랜치내에 소자 분리막용 절연막을 매립하는 단계를 포함한다.The present invention discloses a device isolation method of a semiconductor device with improved surface level difference. The present invention is to reduce the buzz big and surface step according to the conventional Locos technology, the present invention comprises the steps of forming a gate oxide film and a gate electrode film on the semiconductor substrate; Etching the gate electrode film, the gate oxide film, and the semiconductor substrate corresponding to the device isolation region of the semiconductor substrate by a predetermined depth to form a trench; Forming an insulating film for a device isolation film so as to sufficiently fill the resultant of the semiconductor substrate; And etching back the insulating film for device isolation so that the surface of the gate electrode material is exposed, and filling the insulating film for device isolation in the trench.
Description
본 발명은 반도체 디바이스의 소자 분리 방법에 관한 것으로, 보다 구체적으로는 표면 단차가 감소된 반도체 디바이스의 소자 분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly to a device isolation method of a semiconductor device with reduced surface level difference.
집적회로에서 더욱 복잡한 기능 및 높은 실행을 위한 요구가 증대됨에 따라, 액티브 소자의 더욱 밀집됨이 요구된다. 밀도는 다른 트랜지스터와 트랜지스터를 분리하기 위하여 요구된 면적 뿐만아니라, 트랜지스터의 액티브 면적에 의존한다. 아이솔레이션의 일반적인 방법중 하나는 트랜지스터를 국부적으로 성장된 필드 산화에 의하여 분리하는 널리 알려진 로코스 기술이다. 이 기술에 따른 소자 분리 방법은, 먼저 도 1A에 도시된 바와 같이, 반도체 기판(1) 상부에 열산화 방식에 의하여 패드 산화막(2)이 형성되고, 패드 산화막(2) 상부에는 실리콘 질화막(3)이 공지된 화학 기상 증착 방식에 의하여 형성된다. 그 후에, 소자 분리 예정 영역에 해당하는 실리콘 질화막(3)과 패드 산화막(2)은 식각 방식에 의하여 제거한다음, 노출된 반도체 기판 부분은 습식 산화 방식에 의하여 선택적으로 산화되어, 소자 분리막(4)이 형성된다.As the demand for more complex functions and higher performance in integrated circuits increases, more densities of active elements are required. The density depends on the active area of the transistor as well as the area required to separate the transistor from other transistors. One common method of isolation is a well known LOCOS technique that isolates transistors by locally grown field oxidation. In the device isolation method according to this technique, first, as shown in FIG. 1A, a pad oxide film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method, and a silicon nitride film 3 is disposed on a pad oxide film 2. ) Is formed by a known chemical vapor deposition method. Thereafter, the silicon nitride film 3 and the pad oxide film 2 corresponding to the device isolation region are removed by an etching method, and then the exposed semiconductor substrate portion is selectively oxidized by a wet oxidation method, so that the device isolation film 4 is removed. Is formed.
그러나, 상기한 종래의 방법에 따르면, 소자가 형성되어질 면적내로 침투하게 되는 버즈 빅 현상(도면에 X로 표시됨)이 발생되고, 또한, 노출된 반도체 기판이 산화되어 반도체 기판의 표면 상부로 부풀어짐에 따라, 표면 단차가 증대되어, 이후의 공정을 진행하는데 어려움이 존재하였다.However, according to the conventional method described above, a buzz big phenomenon (indicated by X in the figure) occurs that penetrates into the area where the element is to be formed, and the exposed semiconductor substrate is oxidized and swells above the surface of the semiconductor substrate. As a result, the surface step was increased, and there was a difficulty in proceeding with the subsequent process.
본 발명의 목적은, 반도체 디바이스의 소자 분리 방법에 있어서, 소자가 형성되어질 영역으로 확산되는 버즈 빅 현상을 방지할 수 있는 반도체 디바이스의 소자 분리 방법을 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a device separation method of a semiconductor device capable of preventing a buzz big phenomenon in which a device is diffused to a region where a device is to be formed in the device separation method of a semiconductor device.
또한 본 발명의 다른 목적은, 반도체 디바이스의 소자 분리 방법에 있어서, 반도체 디바이스의 표면 단차를 최소화 할 수 있는 반도체 디바이스의 소자 분리 방법을 제공하는 것이다.Another object of the present invention is to provide a device isolation method of a semiconductor device capable of minimizing the surface level of the semiconductor device in the device separation method of the semiconductor device.
도 1A 및 도 1B은 종래의 반도체 디바이스의 소자 분리방법을 설명하기 위한 단면도1A and 1B are cross-sectional views illustrating a device isolation method of a conventional semiconductor device.
도 2A 내지 도 2D은 본 발명의 반도체 디바이스의 소자 분리방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a device isolation method of a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
11- 반도체 기판11A- 반도체 기판의 식각된 면11- Semiconductor Substrates 11A- Etched Surface of Semiconductor Substrate
12- 게이트 절연막13- 폴리실리콘12- gate insulating film 13- polysilicon
14- 소자 분리막15- 도핑된 폴리실리콘막14- Device Separator 15- Doped Polysilicon Film
16- 실리사이드막17- 접합 영역16- silicide layer 17- junction region
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 반도체 기판 상부에 게이트 산화막과 게이트 전극용 막을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 해당하는 게이트 전극용 막, 게이트 산화막 및 반도체 기판의 소정 깊이만큼을 식각하여 트랜치를 형성하는 단계; 반도체 기판의 결과물이 충분히 매립되도록 소자 분리막용 절연막을 형성하는 단계; 상기 소자 분리막용 절연막을 게이트 전극용 물질의 표면이 노출되도록 에치백하여 트랜치내에 소자 분리막용 절연막을 매립하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, the present invention comprises the steps of forming a gate oxide film and a gate electrode film on the semiconductor substrate; Etching the gate electrode film, the gate oxide film, and the semiconductor substrate corresponding to the device isolation region of the semiconductor substrate by a predetermined depth to form a trench; Forming an insulating film for a device isolation film so as to sufficiently fill the resultant of the semiconductor substrate; And etching back the insulating film for device isolation so that the surface of the gate electrode material is exposed, and filling the insulating film for device isolation in the trench.
본 발명에 의하면, 게이트 전극용 폴리실리콘막의 형성후, 트랜치를 형성하고, 그 내부에 플로우 특성이 높은 절연막을 매립시키므로써, 선택적 산화 공정에 따른 버즈빅을 감소시키고, 더불어, 반도체 디바이스의 표면 단차를 최소화한다.According to the present invention, after forming the polysilicon film for a gate electrode, by forming a trench and embedding an insulating film having a high flow characteristic therein, it is possible to reduce buzz big due to the selective oxidation process, and also to increase the surface level of the semiconductor device. Minimize.
[실시예]EXAMPLE
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2A 내지 도 2D는 본 발명의 반도체 소자의 필드 산화 마스크 및 그것의 제조방법을 설명하기 위한 도면이다.2A to 2D are views for explaining a field oxide mask of the semiconductor device of the present invention and a method of manufacturing the same.
먼저, 도 2A에 도시된 바와 같이, 반도체 기판(11) 예를들어, 소자의 형성을 최적화하기 위한 웰(도시되지 않음)과 문턱 전압 조절 이온이 주입된 실리콘 기판상에, 게이트 절연막(12)이 소정 두께로 형성되고, 이어서, 게이트 절연막(12) 상부에 게이트 전극용 폴리실리콘막이 1000 내지 5000Å의 두께로 증착된다.First, as shown in FIG. 2A, a gate insulating film 12 is formed on a semiconductor substrate 11, for example, on a silicon substrate implanted with a well (not shown) and threshold voltage regulating ions for optimizing device formation. This predetermined thickness is formed, and then a polysilicon film for a gate electrode is deposited on the gate insulating film 12 to a thickness of 1000 to 5000 GPa.
도 2B를 참조하여, 폴리실리콘막(13) 상부에는 소자 분리 예정 영역이 노출되도록 마스크 패턴(도시되지 않음)이 형성되고, 마스크 패턴의 형태로 폴리실리콘막(13), 게이트 절연막(12) 및 반도체 기판(11)이 소정 깊이만큼 플라즈마 이방성 식각되어, 트랜치(100)가 형성된다. 그후, 반도체 기판(11)의 식각된 면(11A)에 채널 스톱퍼 이온(도면에 +로 표시됨) 예를들어, P형 기판일 경우, 기판과 동일한 타입의 B등이 이온 주입된다.Referring to FIG. 2B, a mask pattern (not shown) is formed on the polysilicon film 13 to expose the device isolation region, and the polysilicon film 13, the gate insulating film 12, and the like in the form of a mask pattern. The semiconductor substrate 11 is plasma anisotropically etched by a predetermined depth to form the trench 100. Thereafter, channel stopper ions (indicated by + in the figure) are etched into the etched surface 11A of the semiconductor substrate 11, for example, in the case of a P-type substrate, B and the like of the substrate.
그 다음으로, 도 2C에 도시된 바와 같이, 반도체 기판상의 결과물이 충분히 매립되도록, 플로우(flow) 특성이 우수한 소자 분리용 절연막 예를들어, 실리콘 산화막이 CVD 방식에 의하여 증착되고, 소자 분리용 절연막은 게이트 전극용 폴리실리콘(13)의 최상단이 노출될때 까지 에치백되어, 트랜치(100)내에 매립되고, 이로써, 소자 분리막(14)이 형성된다. 이때, 소자 분리막(14)은 반도체 기판 표면으로 부터 게이트 전극용 폴리실리콘막(13)의 높이만큼 돌출된다. 이는 이후에 형성되어질 게이트 전극과의 높이를 최소화하기 위함이다.Next, as shown in Fig. 2C, an insulating film for device isolation having excellent flow characteristics, for example, a silicon oxide film is deposited by a CVD method so that the resultant on the semiconductor substrate is sufficiently embedded, the insulating film for device separation Is etched back until the top end of the polysilicon 13 for gate electrodes is exposed, and is buried in the trench 100, whereby the device isolation film 14 is formed. In this case, the device isolation layer 14 protrudes from the surface of the semiconductor substrate by the height of the polysilicon layer 13 for the gate electrode. This is to minimize the height with the gate electrode to be formed later.
그리고나서, 도 2D에 도시된 바와 같이, 결과물 상부에 도핑된 폴리실리콘막(15)과 이후에 형성되어질 게이트 전극의 전도성을 개선하기 위하여, 금속 실리사이드막(16)이 도핑된 폴리실리콘막(15)이 형성된다. 그후, 폴리실리콘막(13), 도핑된 폴리실리콘막(15), 실리사이드막(16)은 게이트 전극의 형태로 패터닝된 후, 노출된 반도체 기판(11)의 소자 형성 영역에는 접합 영역(17)이 형성된다.Then, as shown in FIG. 2D, the polysilicon film 15 doped with the metal silicide film 16 to improve the conductivity of the doped polysilicon film 15 over the resultant and the gate electrode to be formed thereafter. ) Is formed. Thereafter, the polysilicon film 13, the doped polysilicon film 15, and the silicide film 16 are patterned in the form of a gate electrode, and then a junction region 17 is formed in the element formation region of the exposed semiconductor substrate 11. Is formed.
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 게이트 전극용 폴리실리콘막의 형성후, 트랜치를 형성하고, 그 내부에 플로우 특성이 높은 절연막을 매립시키므로써, 선택적 산화 공정에 따른 버즈빅을 감소시키고, 더불어, 반도체 디바이스의 표면 단차를 최소화한다.As described in detail above, according to the present invention, after forming the polysilicon film for the gate electrode, by forming a trench and embedding an insulating film having a high flow characteristic therein, thereby reducing the buzz big due to the selective oxidation process, In addition, the surface step of the semiconductor device is minimized.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 이 기술에 속하는 당업자에게 자명할 뿐만 아니라 용이하게 발명해낼 수 있다. 따라서 여기에 첨부된 청구범위는 앞서 설명된 것에 한정하지 않고, 하기의 청구범위는 이 발명에 내제되어 있는 특허성 있는 신규한 모든 것을 포함하며, 아울러 이 발명이 속하는 기술분야에서 통상의 지식을 가진자에 의해서 균등하게 처리되는 모든 특징을 포함한다Various embodiments are obvious to those skilled in the art without departing from the spirit and spirit of the invention and can be easily invented. Thus, the claims appended hereto are not limited to those described above, and the following claims are intended to cover all of the patented novelties inherent in this invention, and furthermore to those skilled in the art to which this invention pertains. Includes all features processed by the child evenly
Claims (6)
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| KR100466025B1 (en) * | 2002-04-18 | 2005-01-13 | 동부아남반도체 주식회사 | Method manufacturing semiconductor device having sti structure |
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