KR100214847B1 - Method for isolation of semiconductor device - Google Patents
Method for isolation of semiconductor device Download PDFInfo
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- KR100214847B1 KR100214847B1 KR1019960047572A KR19960047572A KR100214847B1 KR 100214847 B1 KR100214847 B1 KR 100214847B1 KR 1019960047572 A KR1019960047572 A KR 1019960047572A KR 19960047572 A KR19960047572 A KR 19960047572A KR 100214847 B1 KR100214847 B1 KR 100214847B1
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- element isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Abstract
본 발명은 표면 단차가 개선된 반도체 디바이스의 소자 분리 방법이 개시된다. 개시된 본 발명은, 종래의 로코스 기술에 따른 버즈 빅 및 표면 단차를 감소시키기 위한 것으로, 본 발명은 반도체 기판 상부에 게이트 산화막과 게이트 전극용 막을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 해당하는 게이트 전극용 막, 게이트 산화막 및 반도체 기판의 소정 깊이만큼을 식각하여 트랜치를 형성하는 단계; 반도체 기판의 결과물이 충분히 매립되도록 소자 분리막용 절연막을 형성하는 단계; 상기 소자 분리막용 절연막을 게이트 전극용 물질의 표면이 노출되도록 에치백하여 트랜치내에 소자 분리막용 절연막을 매립하는 단계를 포함한다.The present invention discloses a device isolation method of a semiconductor device with improved surface step. SUMMARY OF THE INVENTION The present invention is directed to a method for reducing buzzbugs and surface trenches in accordance with the conventional LOCOS technique, the method comprising: forming a gate oxide film and a gate electrode film on a semiconductor substrate; Etching a gate electrode film, a gate oxide film, and a semiconductor substrate corresponding to a predetermined element isolation region of the semiconductor substrate by a predetermined depth to form a trench; Forming an insulating film for an element isolation film so that a result of the semiconductor substrate is sufficiently embedded; And inserting the insulating film for an element isolation film back into the trench so as to expose the surface of the material for the gate electrode so that an insulating film for the element separation film is buried in the trench.
Description
본 발명은 반도체 디바이스의 소자 분리 방법에 관한 것으로, 보다 구체적으로는 표면 단차가 감소된 반도체 디바이스의 소자 분리 방법에 관한 것이다.The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a device isolation method of a semiconductor device with reduced surface step.
집적회로에서 더욱 복잡한 기능 및 높은 실행을 위한 요구가 증대됨에 따라, 액티브 소자의 더욱 밀집됨이 요구된다. 밀도는 다른 트랜지스터와 트랜지스터를 분리하기 위하여 요구된 면적 뿐만아니라, 트랜지스터의 액티브 면적에 의존한다. 아이솔레이션의 일반적인 방법중 하나는 트랜지스터를 국부적으로 성장된 필드 산화에 의하여 분리하는 널리 알려진 로코스 기술이다. 이 기술에 따른 소자 분리 방법은, 먼저 도 1A에 도시된 바와 같이, 반도체 기판(1) 상부에 열산화 방식에 의하여 패드 산화막(2)이 형성되고, 패드 산화막(2) 상부에는 실리콘 질화막(3)이 공지된 화학 기상 증착 방식에 의하여 형성된다. 그 후에, 소자 분리 예정 영역에 해당하는 실리콘 질화막(3)과 패드 산화막(2)은 식각 방식에 의하여 제거한다음, 노출된 반도체 기판 부분은 습식 산화 방식에 의하여 선택적으로 산화되어, 소자 분리막(4)이 형성된다.As the demand for more sophisticated functions and higher performance in integrated circuits grows, more densification of active devices is required. The density depends on the active area of the transistor, as well as the area required to separate the other transistors and transistors. One common method of isolation is the well-known LOCOS technology, which isolates transistors by locally grown field oxidation. 1A, a pad oxide film 2 is formed on a semiconductor substrate 1 by a thermal oxidation method and a silicon nitride film 3 is formed on a pad oxide film 2 ) Are formed by a known chemical vapor deposition method. Thereafter, the silicon nitride film 3 and the pad oxide film 2 corresponding to the element isolation scheduled region are removed by an etching method, and then the exposed semiconductor substrate portion is selectively oxidized by the wet oxidation method, .
그러나, 상기한 종래의 방법에 따르면, 소자가 형성되어질 면적내로 침투하게 되는 버즈 빅 현상(도면에 X로 표시됨)이 발생되고, 또한, 노출된 반도체 기판이 산화되어 반도체 기판의 표면 상부로 부풀어짐에 따라, 표면 단차가 증대되어, 이후의 공정을 진행하는데 어려움이 존재하였다.However, according to the above-described conventional method, a burzzing phenomenon (indicated by X in the figure) that penetrates into the area where the device is to be formed is generated, and the exposed semiconductor substrate is oxidized and bulges to the upper surface of the semiconductor substrate , The surface step difference was increased, and there was a difficulty in proceeding the subsequent steps.
본 발명의 목적은, 반도체 디바이스의 소자 분리 방법에 있어서, 소자가 형성되어질 영역으로 확산되는 버즈 빅 현상을 방지할 수 있는 반도체 디바이스의 소자 분리 방법을 제공하는 것이다.It is an object of the present invention to provide a device isolation method for a semiconductor device which can prevent a burzzing phenomenon that diffuses into a region where a device is to be formed, in a device isolation method of a semiconductor device.
또한 본 발명의 다른 목적은, 반도체 디바이스의 소자 분리 방법에 있어서, 반도체 디바이스의 표면 단차를 최소화 할 수 있는 반도체 디바이스의 소자 분리 방법을 제공하는 것이다.It is another object of the present invention to provide a device isolation method of a semiconductor device capable of minimizing a surface step difference of a semiconductor device in a device isolation method of a semiconductor device.
도 1A 및 도 1B은 종래의 반도체 디바이스의 소자 분리방법을 설명하기 위한 단면도1A and 1B are cross-sectional views for explaining a device isolation method of a conventional semiconductor device
도 2A 내지 도 2D은 본 발명의 반도체 디바이스의 소자 분리방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views for explaining a device isolation method of a semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명*Description of the Related Art [0002]
11- 반도체 기판11A- 반도체 기판의 식각된 면11-Semiconductor Substrate 11A-The etched side of the semiconductor substrate
12- 게이트 절연막13- 폴리실리콘12-gate insulating film 13 -Polysilicon
14- 소자 분리막15- 도핑된 폴리실리콘막14-element separator 15-doped polysilicon film
16- 실리사이드막17- 접합 영역16-silicide film 17-junction region
상기한 본 발명의 목적을 달성하기 위하여, 본 발명은 반도체 기판 상부에 게이트 산화막과 게이트 전극용 막을 형성하는 단계; 반도체 기판의 소자 분리 예정 영역에 해당하는 게이트 전극용 막, 게이트 산화막 및 반도체 기판의 소정 깊이만큼을 식각하여 트랜치를 형성하는 단계; 반도체 기판의 결과물이 충분히 매립되도록 소자 분리막용 절연막을 형성하는 단계; 상기 소자 분리막용 절연막을 게이트 전극용 물질의 표면이 노출되도록 에치백하여 트랜치내에 소자 분리막용 절연막을 매립하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a gate oxide film and a gate electrode film on a semiconductor substrate; Etching a gate electrode film, a gate oxide film, and a semiconductor substrate corresponding to a predetermined element isolation region of the semiconductor substrate by a predetermined depth to form a trench; Forming an insulating film for an element isolation film so that a result of the semiconductor substrate is sufficiently embedded; And inserting the insulating film for an element isolation film back into the trench so as to expose the surface of the gate electrode material so as to fill the insulating film for the element isolation film.
본 발명에 의하면, 게이트 전극용 폴리실리콘막의 형성후, 트랜치를 형성하고, 그 내부에 플로우 특성이 높은 절연막을 매립시키므로써, 선택적 산화 공정에 따른 버즈빅을 감소시키고, 더불어, 반도체 디바이스의 표면 단차를 최소화한다.According to the present invention, after forming the polysilicon film for the gate electrode, a trench is formed and an insulating film having a high flow characteristic is buried in the trench, thereby reducing buzzbing in the selective oxidation process. In addition, .
[실시예][Example]
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2A 내지 도 2D는 본 발명의 반도체 소자의 필드 산화 마스크 및 그것의 제조방법을 설명하기 위한 도면이다.2A to 2D are views for explaining a field oxidation mask of a semiconductor device of the present invention and a manufacturing method thereof.
먼저, 도 2A에 도시된 바와 같이, 반도체 기판(11) 예를들어, 소자의 형성을 최적화하기 위한 웰(도시되지 않음)과 문턱 전압 조절 이온이 주입된 실리콘 기판상에, 게이트 절연막(12)이 소정 두께로 형성되고, 이어서, 게이트 절연막(12) 상부에 게이트 전극용 폴리실리콘막이 1000 내지 5000Å의 두께로 증착된다.First, as shown in FIG. 2A, a gate insulating film 12 is formed on a semiconductor substrate 11, for example, a well (not shown) for optimizing the formation of a device and a silicon substrate into which a threshold voltage adjusting ion is implanted, A polysilicon film for a gate electrode is deposited on the gate insulating film 12 to a thickness of 1000 to 5000 angstroms.
도 2B를 참조하여, 폴리실리콘막(13) 상부에는 소자 분리 예정 영역이 노출되도록 마스크 패턴(도시되지 않음)이 형성되고, 마스크 패턴의 형태로 폴리실리콘막(13), 게이트 절연막(12) 및 반도체 기판(11)이 소정 깊이만큼 플라즈마 이방성 식각되어, 트랜치(100)가 형성된다. 그후, 반도체 기판(11)의 식각된 면(11A)에 채널 스톱퍼 이온(도면에 +로 표시됨) 예를들어, P형 기판일 경우, 기판과 동일한 타입의 B등이 이온 주입된다.2B, a mask pattern (not shown) is formed on the polysilicon film 13 so as to expose a predetermined element isolation region, and the polysilicon film 13, the gate insulating film 12, The semiconductor substrate 11 is plasma anisotropically etched by a predetermined depth to form the trench 100. [ Then, in the case of a channel stopper ion (indicated by + in the drawing) on the etched surface 11A of the semiconductor substrate 11, for example, in the case of a P-type substrate, B of the same type as the substrate is ion-implanted.
그 다음으로, 도 2C에 도시된 바와 같이, 반도체 기판상의 결과물이 충분히 매립되도록, 플로우(flow) 특성이 우수한 소자 분리용 절연막 예를들어, 실리콘 산화막이 CVD 방식에 의하여 증착되고, 소자 분리용 절연막은 게이트 전극용 폴리실리콘(13)의 최상단이 노출될때 까지 에치백되어, 트랜치(100)내에 매립되고, 이로써, 소자 분리막(14)이 형성된다. 이때, 소자 분리막(14)은 반도체 기판 표면으로 부터 게이트 전극용 폴리실리콘막(13)의 높이만큼 돌출된다. 이는 이후에 형성되어질 게이트 전극과의 높이를 최소화하기 위함이다.Next, as shown in FIG. 2C, a silicon oxide film is deposited by a CVD method, for example, an element isolation insulating film having excellent flow characteristics such that the resultant on the semiconductor substrate is sufficiently embedded, Is etched back until the top of the polysilicon 13 for the gate electrode is exposed and buried in the trench 100, thereby forming the device isolation film 14. At this time, the device isolation film 14 protrudes from the surface of the semiconductor substrate by the height of the polysilicon film 13 for the gate electrode. This is to minimize the height of the gate electrode to be formed later.
그리고나서, 도 2D에 도시된 바와 같이, 결과물 상부에 도핑된 폴리실리콘막(15)과 이후에 형성되어질 게이트 전극의 전도성을 개선하기 위하여, 금속 실리사이드막(16)이 도핑된 폴리실리콘막(15)이 형성된다. 그후, 폴리실리콘막(13), 도핑된 폴리실리콘막(15), 실리사이드막(16)은 게이트 전극의 형태로 패터닝된 후, 노출된 반도체 기판(11)의 소자 형성 영역에는 접합 영역(17)이 형성된다.Then, as shown in Fig. 2D, in order to improve the conductivity of the doped polysilicon film 15 on the resultant structure and the gate electrode to be formed later, a metal silicide film 16 is formed on the doped polysilicon film 15 Is formed. Thereafter, the polysilicon film 13, the doped polysilicon film 15, and the silicide film 16 are patterned in the form of a gate electrode, and then the element formation region of the exposed semiconductor substrate 11 is patterned into the junction region 17, .
이상에서 자세히 설명한 바와 같이, 본 발명에 의하면, 게이트 전극용 폴리실리콘막의 형성후, 트랜치를 형성하고, 그 내부에 플로우 특성이 높은 절연막을 매립시키므로써, 선택적 산화 공정에 따른 버즈빅을 감소시키고, 더불어, 반도체 디바이스의 표면 단차를 최소화한다.As described in detail above, according to the present invention, after formation of a polysilicon film for a gate electrode, a trench is formed and an insulating film having a high flow characteristic is buried in the trench, thereby reducing buzzbing in the selective oxidation process, In addition, the surface step of the semiconductor device is minimized.
본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 이 기술에 속하는 당업자에게 자명할 뿐만 아니라 용이하게 발명해낼 수 있다. 따라서 여기에 첨부된 청구범위는 앞서 설명된 것에 한정하지 않고, 하기의 청구범위는 이 발명에 내제되어 있는 특허성 있는 신규한 모든 것을 포함하며, 아울러 이 발명이 속하는 기술분야에서 통상의 지식을 가진자에 의해서 균등하게 처리되는 모든 특징을 포함한다Various embodiments are obvious to those skilled in the art without departing from the spirit and spirit of the present invention, and can easily be invented. Accordingly, the appended claims are not intended to be limited to the foregoing description, and the following claims are intended to cover all such novelties, which are inherent in the invention, and which have the ordinary skill in the art to which this invention pertains. It includes all features that are treated equally by the person
Claims (6)
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