JPS5617054A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5617054A
JPS5617054A JP9358279A JP9358279A JPS5617054A JP S5617054 A JPS5617054 A JP S5617054A JP 9358279 A JP9358279 A JP 9358279A JP 9358279 A JP9358279 A JP 9358279A JP S5617054 A JPS5617054 A JP S5617054A
Authority
JP
Japan
Prior art keywords
region
type
diffused
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9358279A
Other languages
Japanese (ja)
Inventor
Hiroshi Kanno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9358279A priority Critical patent/JPS5617054A/en
Publication of JPS5617054A publication Critical patent/JPS5617054A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To eliminate all mask matching slips and to obtain a transistor having high density and high performance by forming an active base region, a base wall region and an active base region, an emitter region by a self-matching process using a nitride film and an oxide film. CONSTITUTION:An N-type buried region 2 is diffused on a P-type semiconductor substrate 1, an N-type layer 3 is epitaxially grown on the entire surface, and the layer 3 is formed in an island including the region 2 by the P<+>-type region 4 reaching the substrate 1. Then, an oxide film 12 is coated on the entire surface, is etched to remove the base wall on the active base forming region 13, and a nitride film 14 is coated on the entire surface. Thereafter, openings are sequentially perforated at the film 14, a P-type base wall region 5' is diffused in the layer 3, and an active base region 6' making contact therewith is diffused to form an emitter region 7' in the region 6'. Subsequently, the film 14 is removed, an oxide film 12 is newly coated thereon, an opening 11 for mounting a collector electrode is perforated thereat, and an N<+>-type collector electrode pickup region 8' is diffused in the layer 3.
JP9358279A 1979-07-20 1979-07-20 Manufacture of semiconductor device Pending JPS5617054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9358279A JPS5617054A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9358279A JPS5617054A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5617054A true JPS5617054A (en) 1981-02-18

Family

ID=14086260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9358279A Pending JPS5617054A (en) 1979-07-20 1979-07-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5617054A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59147455A (en) * 1983-02-10 1984-08-23 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508489A (en) * 1973-05-21 1975-01-28

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS508489A (en) * 1973-05-21 1975-01-28

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59147455A (en) * 1983-02-10 1984-08-23 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH0313746B2 (en) * 1983-02-10 1991-02-25 Matsushita Electric Ind Co Ltd

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