JPS5541787A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5541787A
JPS5541787A JP11616378A JP11616378A JPS5541787A JP S5541787 A JPS5541787 A JP S5541787A JP 11616378 A JP11616378 A JP 11616378A JP 11616378 A JP11616378 A JP 11616378A JP S5541787 A JPS5541787 A JP S5541787A
Authority
JP
Japan
Prior art keywords
island
region
type
transistor
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11616378A
Other languages
Japanese (ja)
Inventor
Teruo Kusaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11616378A priority Critical patent/JPS5541787A/en
Publication of JPS5541787A publication Critical patent/JPS5541787A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0664—Vertical bipolar transistor in combination with diodes

Abstract

PURPOSE: To provide a semiconductor device wherein a monocrystal layer island separated by a dielectric is provided on a polycrystal Si supporter layer, and a transistor and a diode are formed in said island thereby to lower the gain of an inter-element parasitic transistor but not to lower greatly the integrated density thereof.
CONSTITUTION: On a polycrystal Si supporter layer 4 there is provided an N-type Si monocrystal island 1 while being separated by a SiO2 film 5, and at one side of said island 1 there are diffusion-formed an N-type emitter region 2a and a P-type base region 2b thereby to form an NPN transistor 2 by use of the island 1 in a cathode region. At the other side of the island 1 there is formed a diode 3 having a P- type anode region 3a using the island 1 in the cathode region, and a P-type separated region 6 is diffusion-formed between the transistor 2 and the diode 3. Thereafter, at both sides of the region 6 N+-type regions 7 contacting the same are provided, and the regions 6 and 7 are connected to each other by a conductor metal 8. By this procedure, a parasitic transistor effect between the circuit elements is reduced.
COPYRIGHT: (C)1980,JPO&Japio
JP11616378A 1978-09-20 1978-09-20 Semiconductor device Pending JPS5541787A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11616378A JPS5541787A (en) 1978-09-20 1978-09-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11616378A JPS5541787A (en) 1978-09-20 1978-09-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5541787A true JPS5541787A (en) 1980-03-24

Family

ID=14680329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11616378A Pending JPS5541787A (en) 1978-09-20 1978-09-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5541787A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3013080U (en) * 1994-12-27 1995-06-27 英夫 逸見 Ladder
JP3024686U (en) * 1995-11-15 1996-05-31 関東梯子株式会社 Mechanism to prevent biting of the holding metal fitting piece in the hanging metal fitting attached to the third ladder of the triple ladder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3013080U (en) * 1994-12-27 1995-06-27 英夫 逸見 Ladder
JP3024686U (en) * 1995-11-15 1996-05-31 関東梯子株式会社 Mechanism to prevent biting of the holding metal fitting piece in the hanging metal fitting attached to the third ladder of the triple ladder

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