JPS54106175A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54106175A
JPS54106175A JP1386678A JP1386678A JPS54106175A JP S54106175 A JPS54106175 A JP S54106175A JP 1386678 A JP1386678 A JP 1386678A JP 1386678 A JP1386678 A JP 1386678A JP S54106175 A JPS54106175 A JP S54106175A
Authority
JP
Japan
Prior art keywords
type
layer
poly
drilled
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1386678A
Other languages
Japanese (ja)
Inventor
Norio Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP1386678A priority Critical patent/JPS54106175A/en
Publication of JPS54106175A publication Critical patent/JPS54106175A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To reduce the space between the emitter and the base and thus to enhance the high frequency characteristics for the high frequency transistor featuring the doped poly silicon structure by using the coarse pattern for etching of the poly- crystal Si layer and the fine pattern for etching of the Al electrode respectively.
CONSTITUTION: N--type layer 2 is epitaxial-grown on N+-type Si substrate 1 and covered with SiO2 film 4 with opening 3 drilled and to form two P+-type regions 5 to feature the graft base structure. Then opening 6 is drilled covering over two regions 5 including the SiO2 film grown then, and then shallow P-type base region 7 between these regions. After this, the entire surface is covered with SiO2 film 8 with opening 9 and 10 drilled, and then poly-crystal Si layer 11 and N-type poly-crystal Si layer 12 are laminated and grown on the entire surface. Then mask pattern 17 is provided to form shallow N-type emitter region 14 within region 7 through diffusion and with use of the coarse pattern for the mask. Then the fine pattern is used to form Al base and emitter electrodes 15 and 16.
COPYRIGHT: (C)1979,JPO&Japio
JP1386678A 1978-02-09 1978-02-09 Manufacture of semiconductor device Pending JPS54106175A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1386678A JPS54106175A (en) 1978-02-09 1978-02-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1386678A JPS54106175A (en) 1978-02-09 1978-02-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54106175A true JPS54106175A (en) 1979-08-20

Family

ID=11845158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1386678A Pending JPS54106175A (en) 1978-02-09 1978-02-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54106175A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5094964A (en) * 1989-05-02 1992-03-10 Kabushiki Kaisha Toshiba Method for manufacturing a bipolar semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5094964A (en) * 1989-05-02 1992-03-10 Kabushiki Kaisha Toshiba Method for manufacturing a bipolar semiconductor device

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