JPS5496975A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5496975A
JPS5496975A JP399378A JP399378A JPS5496975A JP S5496975 A JPS5496975 A JP S5496975A JP 399378 A JP399378 A JP 399378A JP 399378 A JP399378 A JP 399378A JP S5496975 A JPS5496975 A JP S5496975A
Authority
JP
Japan
Prior art keywords
region
base
emitter
type
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP399378A
Other languages
Japanese (ja)
Inventor
Sadayuki Hamada
Koichiro Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP399378A priority Critical patent/JPS5496975A/en
Publication of JPS5496975A publication Critical patent/JPS5496975A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To obtain a lateral transistor which features a high emitter-earthed current amplification factor and good frequency characteristics by forming a high impurity density region which is the same conducting type as the base different from the buried layer right under the emitter within the base region or right under the base draw-out impurity region.
CONSTITUTION: N+-buried layer 13 is formed through diffusion on P-type Si substrate 11, and N-type layer 12 to become the base region is epitaxial-grown on the entire surface with its surface covered with SiO2 film 14. Then the window is drilled to film 14 in a smaller size than the emitter region and the base draw-out high density impurity region and enclosing these regions completely in order to inject the impurity ion. Thus, N+-buried region 15 is formed through the heat treatment. After this, the window is drilled again at the emitter and collector forming regions to form P-type emitter region 16 and P-type collector region 17 through diffusion with base electrode draw-out region 18 added. Then Al wiring 19 is coated to each region to form a lateral transistor.
COPYRIGHT: (C)1979,JPO&Japio
JP399378A 1978-01-17 1978-01-17 Semiconductor device Pending JPS5496975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP399378A JPS5496975A (en) 1978-01-17 1978-01-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP399378A JPS5496975A (en) 1978-01-17 1978-01-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5496975A true JPS5496975A (en) 1979-07-31

Family

ID=11572530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP399378A Pending JPS5496975A (en) 1978-01-17 1978-01-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5496975A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63216374A (en) * 1987-03-04 1988-09-08 Nec Corp Lateral semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63216374A (en) * 1987-03-04 1988-09-08 Nec Corp Lateral semiconductor device

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