JPS5529187A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5529187A
JPS5529187A JP10352678A JP10352678A JPS5529187A JP S5529187 A JPS5529187 A JP S5529187A JP 10352678 A JP10352678 A JP 10352678A JP 10352678 A JP10352678 A JP 10352678A JP S5529187 A JPS5529187 A JP S5529187A
Authority
JP
Japan
Prior art keywords
region
type
layer
film
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10352678A
Other languages
Japanese (ja)
Inventor
Toru Suganuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10352678A priority Critical patent/JPS5529187A/en
Publication of JPS5529187A publication Critical patent/JPS5529187A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE: To eliminate influences of atmosphere on the conjunction surface by providing in advance an insulative film around the side of the conjunction when forming pn conjunction in semiconductor substrate.
CONSTITUTION: P+-type insertion regions 3 and 2 are diffusion-formed respectively at the center portion and both sides of a P-type Si substrate, and an N-type layer 5, which becomes a collector, is epitaxially grown on the entire surface. A P2-type region 4 corresponding to the region 2 was diffusion-formed and cnnected to the region 2 to separate a layer 5 in the form of island. Thereafter, a P-type base region 6 is diffusion-formed in the layer 5 by use of a photoresist mask, and in a SiO2 film 9 formed at this time, a given size of opening is provided. Then, on a part of the remaining film 9 and the opening, a Si3N4 film 19 is vapor-deposited and heat- treated to form thick SiO2 films 10 and 11 in the exposed region 6 and the layer 5. Thereafter, an N-type emitter region 7 is diffusion-formed at the region surrounded by the layer 10 in the region 6, and an N+-type electrode lead region 8 is diffuion- formed in the region surrounded by the film 11.
COPYRIGHT: (C)1980,JPO&Japio
JP10352678A 1978-08-24 1978-08-24 Production of semiconductor device Pending JPS5529187A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10352678A JPS5529187A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10352678A JPS5529187A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5529187A true JPS5529187A (en) 1980-03-01

Family

ID=14356347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10352678A Pending JPS5529187A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5529187A (en)

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