JPS55132053A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS55132053A JPS55132053A JP3854979A JP3854979A JPS55132053A JP S55132053 A JPS55132053 A JP S55132053A JP 3854979 A JP3854979 A JP 3854979A JP 3854979 A JP3854979 A JP 3854979A JP S55132053 A JPS55132053 A JP S55132053A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- selectively
- ion
- implanted
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a high-integrated device with high yield through a simplified process by a method wherein an epitaxial layer on a p-type Si is isolated to an island region having a buried oxidized film partly, B-ion is implated therein, an As-added polycrystalline-Si is accumulated selectively, and B and As are subjected to thermal diffusion. CONSTITUTION:An n-epitaxial layer 43 is formed on a p<->-type Si substrate 41 is which an n<+>-layer 42 is buried selectively. A double layer of SiO245 and Si3N446 is formed selectively, B-ion is then implanted by means of a resist mask to form a p<+>-isolated layer 44, and a buried oxidized film 47 is formed consecutively through wet oxidation. An opening is provided on a collector layer and an n<+>-layer 48 is formed through P-diffusion. Next, B-ion is implanted on the overall surface and a p-type internal base 49 is formed through thermal diffusion. Then, the layers 46, 45 are removed, an As-added polycrystalline-Si 50 is accumulated selectively, oxidized films 511, 522 are formed at low temperature, B-ion is then implanted to heat treatment, and thus a p<+>-type external base 52 and an n<+>-emitter 53 are formed. A window is provided selectively and an electrode is applied finally. According to this method, the emitter area can be limited, and the emitter base short circuit can be prevented, thus ensuring a high integration at high yield.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3854979A JPS55132053A (en) | 1979-03-31 | 1979-03-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3854979A JPS55132053A (en) | 1979-03-31 | 1979-03-31 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55132053A true JPS55132053A (en) | 1980-10-14 |
Family
ID=12528363
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3854979A Pending JPS55132053A (en) | 1979-03-31 | 1979-03-31 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55132053A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144167A (en) * | 1983-02-07 | 1984-08-18 | Hitachi Ltd | Semiconductor resistance device |
JPS60147154A (en) * | 1983-12-29 | 1985-08-03 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | Resistance structure |
-
1979
- 1979-03-31 JP JP3854979A patent/JPS55132053A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59144167A (en) * | 1983-02-07 | 1984-08-18 | Hitachi Ltd | Semiconductor resistance device |
JPS60147154A (en) * | 1983-12-29 | 1985-08-03 | インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション | Resistance structure |
JPH0531307B2 (en) * | 1983-12-29 | 1993-05-12 | Intaanashonaru Bijinesu Mashiinzu Corp |
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