JPS59144167A - Semiconductor resistance device - Google Patents

Abstract

PURPOSE:To reduce an element in size by forming the first conductive type semiconductor layer of high density directly under the second conductive type layer, thereby forming a high resistance of small pattern without altering a diffusing process. CONSTITUTION:A high density n<+> type buried layer 6 in which n type impurity is previously diffused is formed between an Si substrate 5 and an n type Si layer 1. A doner having large diffusion velocity is diffused in the layer 1 from the layer 6 to form a high density n type layer 7, and part is superposed and formed in a p type region 2. In this manner, the depth of the region 2 is substantially reduced in depth to increase the pinch resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor diffused resistors, and more particularly to pinch type resistor devices.

In a bipolar IC, as shown in Fig. 1, a p-type head region 2 is formed in an epitaxially grown n-type semiconductor layer 1 using base diffusion of an npn transistor, and a shallow height is formed on a part of its surface using emitter diffusion. A diffused resistor which has a high resistance by forming a concentration n+ type region and sandwiching the p-type head region 2 between upper and lower n-type layers is generally known as a pinch resistor. In this pinch resistor, the n+ type region 3 voltage is V as shown in the figure. By applying C, the depletion layer 4 extends within the p-type region 2, narrowing the passage in the direction of the arrow (current flow direction) and controlling the current.

In order to further increase this pinch resistance, (1) make the p-type region shallower, (2) make the n-type region deeper, (3) p
Possible measures include reducing the concentration of the type head region and (4) increasing the size of the p-type head region, but these methods change the diffusion specifications and patterns, and the base diffusion and emitter of the npn transistor As long as diffusion is used as is, there are some problems with the above specification changes, (4)
In this case, the chip area for the resistor region has increased.

The present invention was made to solve the above-mentioned problems, and its purpose is to provide a high resistance transistor without changing the diffusion specifications of a normal NPN transistor and without increasing the chip area. be.

To achieve the above purpose, the pinch type resistor is made by creating a high resistivity region by introducing n-type impurities from below or above into the p-type region directly under the n+-type region or a part thereof by emitter diffusion, and increasing the resistance. It is something.

Hereinafter, a detailed explanation will be given along with examples.

In FIG. 3, one example of a pinch type resistor according to the present invention is shown. In the same figure, 1 is a low concentration epitaxial n
In the Si layer, 2 is a p-type region using base diffusion of an npn transistor, and the diffusion depth d is, for example, 2.7 μm. 3 uses the emitter diffusion of the same transistor.
The + type region and diffusion depth d are approximately 1.7 μm5.
is a p-type Si substrate, and a high concentration n++ buried layer 6 in which n-type impurities such as sb are diffused in advance is formed between the Si substrate 5 and the n-type Si layer 1. 7 is n++ buried layer 6
It is a highly doped n-type layer in which a donor (n-type impurity) with a high diffusion rate such as P ('Jn) is diffused into the n-type S1 layer 1, and a part of it is in the p-type region 2, for example, d3=0. They overlap by about 2 μm.

As described above, according to the present invention, the depth of the p-type region 2 is made substantially shallow by introducing and diffusing the n-type impurity from below the p-type region, thereby meeting the specifications for diffusion of the p-type region and the n+-type region. The resistance of the pinch resistor can be increased without modification. FIG. 4 shows an impurity concentration profile corresponding to FIG. 3.

FIG. 5 shows that instead of diffusing impurities from below, P (phosphorous) impurities are ion-implanted deeply into the surface of the n-type region 3, so that the upper side of the p-type region 2 directly below the n+-type region 3 has a high concentration of n An example in which a mold layer 8 is formed will be shown. In this case as well, the substantial depth of the p-type region 2 becomes shallow due to the overlap d4 of the highly doped n-type layer 8 on the p-type region 2, and the pinch can be applied without changing the specifications of the p-type region or n+ type region diffusion. The resistance can be increased. FIG. 6 shows an impurity concentration profile corresponding to FIG.

In recent years, a process in which a linear section mainly consisting of bipolar elements and IIL (injection integrated logic) coexist has become common, and n+
+ A technique is used in which P (phosphorus) is buried in a buried layer or P (phosphorus) is ion-implanted deeply from the surface of an epitaxial layer. By applying the present invention to such an IIL linear coexistence process, an extremely high pinch resistance can be realized without changing or adding to the existing process. Incidentally, a pinch resistor that performs impurity diffusion from directly below the n+ type region or ion implantation from above can provide a resistance 5 to 10 times higher than a conventional pinch resistor that does not do this even with the same area. Furthermore, by selecting the dose of phosphorus diffusion from the n++ buried layer and the ion implantation from above, pinch resistors having various resistance values can be obtained with the same pattern.

FIG. 7 shows a case where an npn (npn) transistor, a pinch resistor, and an IIL are formed on one semiconductor substrate. In this case, by using the P (phosphorus) resistance from the n++ buried layer, the series resistance of the collector extraction part of the npn) transistor can be reduced, a higher resistance can be obtained with the pinch resistance, and the opposite is achieved with the IIL. (npn) transistor's inverse hFE (βi) can be increased.

According to the present invention described in the embodiments above, the depth of the p-type region is regulated by the compensation effect of the n-type impurity, and high resistance can be achieved with a small pattern without changing the diffusion process for forming other elements. The size can be reduced (by about half or more), resulting in various effects such as easier circuit design.

The present invention is particularly effective when applied to linear IIL coexistence ICs.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a longitudinal sectional view showing an example of a pinch resistor, and FIG. 2 is a plan view, the AA' cross section of which corresponds to FIG. 1. FIG. 3 is a longitudinal sectional view showing an example of a pinch resistor according to the present invention, and FIG. 4 is an impurity concentration distribution curve diagram at the BB section in FIG. 3. FIG. 5 is a vertical cross-sectional view showing another example of the pinch resistor according to the present invention. FIG. 6 is an impurity concentration distribution curve diagram at the c-c' section of FIG. - It is a model sectional view of an example when applied to an IIL coexistence IC. 1...nWsi layer (epitaxial layer), 2...p
Type head area (base), 3...n+ type area emitter),
4... Depletion layer, 5... P-type Si substrate, 6... n
++buried layer, 7...high concentration n-type layer, 8...n-type well. Figure 1 Figure 2 Figure 3 Figure 1 β, Figure 4 δ

Claims (1)

[Claims] 1. A second conductive type semiconductor layer is formed on a first conductive type semiconductor layer, a first conductive type semiconductor layer is formed in a part of the region of the second conductive type semiconductor layer, and a second conductive type semiconductor layer is formed on a second conductive type semiconductor layer. A semiconductor resistance device in which both ends of a conductive type semiconductor are terminals and a first conductive type semiconductor layer is also used as one terminal, the semiconductor resistive device having a highly concentrated first conductive type semiconductor layer directly below the second conductive type layer. 2. The semiconductor resistance device according to claim 1, wherein the first conductivity type layer and a deeper first conductivity type layer are formed in a part of the second conductivity type layer.