JPS62203347A - Semiconductor position detector - Google Patents

Abstract

PURPOSE:To suppress the effect of the surface of a semiconductor inflicting on a resistance layer by a method wherein the P-N junction between a semiconductor base and the resistance layer is used by biasing reversely. CONSTITUTION:A P-type high resistivity region 2 is formed on the main surface on the upper side of an N-type high resistivity Si substrate 1, and N-type or N<+> type surface region 6 is formed thereon. Both ends of the region 2 are contacted to P<+> type low resistivity regions 4 and 5. A current lead-out structure, to be used for photo detection, is formed on the electrodes 14 and 15 located on the regions 4 and 5. The main surface of the substrate 1 is protected by an insulating film 7. An N<+> type low resistivity region 3 is formed on the back surface of the surface 1, and an electrode 13 is formed thereon. The P-N junction between the resistance layer 2 and the semiconductor substrate 1 is reversely biased when the position detecting device is used, and a light spot is made incident from the surface of a semiconductor. A depletion layer is developed in the vicinity of the P-N junction by the reverse bias, but almost no electric field is generated, because the resistance layer 2 is buried in the semiconductor by an isolation layer 6. Even when an electrification is generated on the surface of the semiconductor, the effect inflicted by the resistance layer 2 is small, because the isolated layer 6 performs the function as a shielding against the resistance layer 2.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor device detection device.

(Prior art) As a typical device detection device, a resistive layer made of an impurity-doped layer is formed in a semiconductor substrate such as silicon, and optically excited carriers are generated in this resistive layer.
A semiconductor device detection device is known that detects a light incident device by extracting these carriers from both ends of a resistive layer.

A one-dimensional device detection device will be explained as an example.

For example, a high resistivity P-type paper layer is formed within the surface of an N-type high resistivity silicon substrate. P+ type formation resistivity regions for forming electrodes are provided at both ends of this P-shaped paper layer, and both current extraction electrodes are formed thereon.

An N+ type low resistivity region for electrode formation is provided on the back surface of the N type substrate, and a bias electrode is formed thereon.

The P-shaped paper layer has an elongated shape suitable for one-dimensional device detection applications.

With the PN junction between the N-type substrate and the P-type paper layer being reverse biased, signal light is incident on the vicinity of this PN junction. The photo-excited carriers flow according to the reverse bias, with holes flowing to the P-type paper layer and electrons flowing to the N-type substrate. Since the P-shaped paper layer has current extraction electrodes at both ends thereof, a hole current flows through both electrodes in inverse proportion to the resistance value from the light incident device to each electrode.

If the resistance distribution of the resistive layer is uniform, the resistance at each electrode from the light incidence device is proportional to its distance 'l+I2. Therefore, if the current taken out from each electrode is r,,I2, then 1+/I2-/! 2/l11. Now total length 11+! 2=1. If the distance from the center is represented by X including the sign, then 11= (L/2) 4- x/! 2=(L/2) x. Then, x=(β+12)I2, and (II I2) / (11+12
)=(11-I2)/(7!1+j!2), x=((it+12)I2)・((ItT
2)/(II +12)) -L/2・[(It I2)/(II+12)] It can be expressed as follows.

The device detection accuracy of such a device detection device is as follows: ■) The resistance of the shaped resistive layer is uniformly distributed along the device detection direction;
It relies on current flowing in inverse proportion to resistance.

Forming such a resistance layer requires highly accurate impurity doping. Furthermore, since the resolution of device detection depends on the ability to differentially detect a pair of currents, it is desirable that the value of the resistance layer be high to some extent. Ion implantation technology serves this purpose in that it allows precise control of impurity doping per unit area.

(Problems to be Solved by the Invention) In the semiconductor device detection device as described above, if the resistivity of the resistive layer changes, the device detection accuracy will change.

Semiconductor surfaces are unstable and susceptible to contamination1, so they are protected with passivation films such as oxide films and sealing resins. However, these passivation films and sealing resins also contain trace amounts of impurities such as ionic impurities. When the PN junction of a semiconductor device detection device is reverse biased with a voltage of several volts or more, lines of electric force are formed from the N shadow region kept at a positive potential to the P shadow region kept at a negative potential.

These electric lines of force pass through the passivation film and sealing resin, separating the impurities present there (e.g. NaCj2) into positive and negative ions (e.g. Na+ and Tor). The ions are arranged near the N shadow region. As a result, the charges arranged on the semiconductor surface induce adverse carriers to the surface of the semiconductor region under the passivation film.

Therefore, the resistivity of the resistive layer changes regardless of the impurity concentration, and the device detection accuracy of the semiconductor device detection bag τ decreases.

Further, the semiconductor surface (interface with the insulating film) has poor crystallinity and the presence of surface states, etc., which tends to cause noise and the like.

The above-mentioned problem is caused by the fact that the resistive layer and the PN junction around it are exposed to the semiconductor surface.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device detection device in which a resistance layer is less susceptible to if-'J on a semiconductor surface.

(Means for Solving the Problems) A semiconductor device detection device according to the present invention provides a separation layer of a conductivity type opposite to that of the resistance between the surface of the semiconductor substrate and the resistance layer,
The structure is such that the resistance layer is separated from the semiconductor surface.

From another point of view, this means that the resistive layer is formed from internal regions that do not contain unstable semiconductor surfaces.

Furthermore, in the present invention, the separation layer is electrically connected to the semiconductor substrate. That is, the semiconductor substrate and the separation layer of the same conductivity type are overlapped to form a continuous region.

This keeps the separation layer at the same potential as the semiconductor substrate.

Therefore, even if the PN junction under the separation layer is reverse biased, electric lines of force are prevented from leaking onto the semiconductor surface.

The resistive layer and the spacing layer may be formed by double impurity doping from the same surface of the semiconductor substrate, or the epitaxial layer forming the spacing layer may be grown on the underlying semiconductor substrate on which the resistive layer is formed.

21. Diffusion, ion implantation, etc. are suitable for 21-ping, and ion implantation is particularly suitable for its controllability.

When an epitaxial layer is used, there is an advantage that the impurity concentration of the separation layer can be freely selected.

In use, the PN junction between the resistive layer and the semiconductor body (and standoff layer) is reverse biased and the light spot is incident from the semiconductor surface.

A depletion layer develops near the PN junction () due to the reverse bias, but since the resistance layer is buried within the semiconductor by the separation layer, almost no electric field is generated on the semiconductor surface.

There is a current extraction structure at both ends of the resistance layer, where the PN junction is exposed to the semiconductor surface, but this has little effect on the resistance layer.

Even if charging occurs on the semiconductor surface on the separation layer, the separation VA layer serves as a shield for the resistance layer, so the resistance layer is not affected much.

The spacing layer is also made of the same material as the semiconductor body and absorbs incident light. This is especially true when the impurity concentration is high. Since optically excited carriers generated when no electric field is generated due to a reverse bias do not contribute much to the output signal, the impurity concentration and thickness of the separation layer are preferably selected so as not to increase ineffective light absorption.

For example, the impurity concentration is high and the thickness is sufficiently thin. If the isolation layer is completely depleted due to reverse bias, the electric field will reach the semiconductor surface, which is undesirable.

On the other hand, by embedding the resistive layer in the semiconductor, PN junctions are formed above and below the resistive layer, increasing the effective area for photodetection. Therefore, the photodetection output can be increased, and the ineffective light absorption within the separation layer can be sufficiently compensated for.

In particular, when the separation layer is formed from an epitaxial layer,
Since the impurity concentration of the separation layer can be freely selected, the characteristics of the PN junction above the resistance layer can also be optimized for photodetection.

(Example) The present invention will be explained in more detail with reference to the drawings and the like.

FIGS. 1(a) and 1(b) show an embodiment of a semiconductor device detection apparatus according to the present invention.

A P-type high resistivity region 2, which is a second conductivity type resistance layer, is formed on the upper main surface of the N-layer high resistivity silicon substrate 1, which is a semiconductor substrate of the first conductivity type. An N type or N+ type back surface region 6 which is a type separation layer is formed.

Both ends of the P shadow region 2 are in contact with the P+ type low resistivity regions 4 and 5. These P+ shaped areas J54.5 are connected to the electrode 14 thereon.
．． Together with 15, it forms a current extraction structure for photodetection.

The main surface of the silicon substrate 1 is an insulator 1 such as silicon oxide! J
7 is protected. This insulating film 7 has at least a resistance r
The upper part of FJ2 is made of a material that is transparent to the incident light. An N+ type low resistivity region 3 is formed on the lower main surface (back surface) of the silicon substrate 1, and an electrode 13 is formed thereon.

As shown in the upper surface pattern of FIG. 1(1)l, the N-type separation layer 6 is preferably formed to cover the entire surface of the resistance layer 2 and to be continuous with the N-type silicon substrate 1.

By covering the entire surface of the P-type resistance layer 2 with the N-type separation layer,
The PN junction 12 around the shaped resistive layer is completely embedded in the semiconductor as shown in FIG. 1<C1.

N-type silicon substrate 1 and N (N”) around resistive layer 2
Since the separation layer is kept at a constant potential, the electric field around the PN junction 12 does not leak onto the semiconductor surface.

The P+ type region 45 for current extraction is exposed on the semiconductor surface, and the PN junction around it is also exposed on the semiconductor surface. Therefore, the current extraction structure (4, 14>(5,
15) An electric field is generated on the semiconductor surface in the vicinity, and electric lines of force are generated.

However, since the resistive layer 2 and the exposed ends of these PN junctions are separated, the influence on the resistive layer 2 is small.

Furthermore, even if ions move to the upper part of the resistance layer 2 due to a slight leakage of electric lines of force, in this embodiment, they are negative ions on the N-type separator 6, and their γ-effects are also N-type.
It is electrically shielded by the shape separation layer 6.

Therefore, even if a reverse bias is applied for a long period of time, the resistance of the resistance layer 2 hardly changes. Note that, as shown in FIG. 1b, by forming the N+ type separation layer 6 so as to penetrate into the P+ type region 45, the PN
It is also possible to reduce the effects of exposed joint edges.

The silicon substrate l is, for example, N type, 5xl□+tcm4
The depletion layer should be extended sufficiently.

The upper surface shape of the resistance layer 2 of the one-dimensional detection device is preferably rectangular, for example, a rectangle of 1 mm x 3 mm. The depth and impurity concentration of the resistance layer 2 are selected so that it is not completely depleted by reverse bias, provides an appropriate resistance value (for example, on the order of 100Ω), and provides a sufficiently wide effective light absorption region. Good. For example, 0.3 p m thickness, 5 X I
015cm-3 is used.

The spacing J'56 substantially covers the resistive layer 2, shielding it electrically and causing less ineffective light absorption. For example, impurity concentration l Q” cm−3,
The depth shall be 0.2.17 m.

The N+ type contact layer 3 on the back surface is a region on which an electrode is formed, and may be made to have a sufficiently low resistivity. For example, it can be created by diffusion after or before the formation of the front side impurity doped region.

The P+ type low resistivity region 4.5 on the front side is also a region for forming an electrode thereon, but at the same time it becomes a region defining both ends of the P type resistor I'i2.

For example, the resistor Ft2 and the separation layer 6 can be formed by diffusion.

The resistive layer 2 and #1 layer 6 determine the resistance of the resistive layer 2, and are preferably formed under precise control.

For example, the resistor Fj2 can be made by boron ion implantation, and the separation layer 6 can be made by phosphorus or arsenic ion implantation.

To create a shallower layer, laser annealing or the like may be used in which the semiconductor surface is melted using a laser in an inert gas atmosphere.

An example of impurity distribution within a silicon substrate is shown in FIG. The horizontal axis indicates the depth from the front surface to the back surface, and the vertical axis indicates the impurity concentration. N
The shape separation layer 6 is a phosphorus ion-implanted layer with a surface concentration of IQ.
'8cm-'', depth 0.2pm, P-type resistance layer 2 is a poron ion implantation layer with a surface concentration of 5X 1016c.
m-3, depth 0.5 μm, N type substrate 1 thickness 200 μm
, the undoped N+ type region 3 of the silicon wafer with an impurity concentration of 5 x 101'' cm-3 is a phosphorous diffusion layer with a surface concentration of 5 x 1019 cm'''3. Depth 0.8p
It is m.

An example of the manufacturing method will be described below. After forming a P+ type region 45 in the surface of the N type high-resistance silicon substrate 1 by diffusion, boron ions were implanted through a mask at an acceleration voltage of 150 KeV and a line of 1R2 x 10" cm ' at 900°C for 30 minutes.
The P-type resistance layer 2 is formed by annealing for a minute.

A mask with a shape that wraps around the fAP type resistance layer 2 is made, and phosphorus ions are accelerated through this mask at a voltage of 150 KeV.
Implant with dose 2x 1014 cm-2, 3 at 850℃
Anneal for 0 minutes. As a result, a P-type resistance layer 2 covered with an N-type &11 barrier layer 6 is formed.

After that, a normal electrode attaching process is performed, as shown in FIG. 1(a).

The semiconductor device detection device shown in FIG. 1(b) is obtained.

The thus obtained semiconductor device detection device was heated to a temperature of 85°C.
As a result of testing for 2000 hours at a humidity of 85% and a bias voltage of 15V, there was hardly any deterioration in the detection accuracy of the device or any change in the resistance between the electrodes, which was observed in conventional devices.

FIG. 3 shows a semiconductor device detection apparatus according to another embodiment.

In the embodiment of FIG. 1(a) and FIG. 1(bl), the isolation layer was formed by doping impurities from the semiconductor surface, but in this embodiment, after forming the P-type resistor Fi2, an N-type epitaxial layer was formed on it. The separation Pi6 is formed by growing.

Thereafter, electrode extraction regions 4.5 are formed by diffusing P-type impurities. The other parts are shown in Figure 1(a).
Similar to the embodiment in Figure C: b).

In the case of this embodiment, since the N-type separation Fi 6 is formed by epitaxial growth, the impurity concentration of the separation layer 6 can be lower than the impurity concentration of the resistance layer 2 .

The P-type resistance layer 2 is almost completely surrounded by the N shadow region with a low impurity concentration, and the entire surrounding PN junction can be used as an effective photodetection region.

Furthermore, the impurity concentration of the separation layer 6 can be lowered, which is effective in reducing ineffective light absorption.

(Effects of the Invention) As described above in detail, the semiconductor device detection device according to the present invention has a configuration in which a separation layer opposite to the resistance is provided between the semiconductor substrate surface and the resistance layer, and the resistance layer is separated from the semiconductor surface. It becomes.

Therefore, the resistance layer is less affected by the semiconductor surface and operates stably.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a sectional view and a top pattern view of an embodiment of a semiconductor device detection apparatus according to the present invention. FIG. 2 is a graph showing an example of an impurity concentration profile. FIG. 3 is a sectional view of another embodiment of the semiconductor device detection apparatus according to the present invention. 1...N type semiconductor substrate 2...P type resistor layer 3...N+ type low resistivity region 4.5......P+ type paper resistivity Area 6...
N-type separation stone 7... Insulating film patent applicant Hamamatsu Photonics Co., Ltd. Agent Patent attorney Inoro Groove piece 1 (a) Figure 2 Figure 3. l Procedural amendment (Holiki M Ro June 3, 1961)

Claims (7)

[Claims] (1) A semiconductor substrate of a first conductivity type, a resistance layer of a second conductivity type formed within the main surface of the semiconductor substrate, and a pair of current extraction structures formed at both ends of the resistance layer. ,
a separation layer of a first conductivity type formed within the main surface of the semiconductor substrate between the resistance layer and the main surface, the PN junction between the semiconductor substrate and the resistance layer being reverse biased; A semiconductor device detection device characterized in that it is used as a semiconductor device. (2) The semiconductor device detection device according to claim 1, wherein the separation layer extends to and is electrically connected to the first conductivity type portion of the semiconductor substrate. (3) The semiconductor device detection device according to claim 1 or 2, wherein the separation layer has a depth of about several μm. (4) The first conductivity type is N type, the second conductivity type is P type, and both the resistance layer and the separation layer are layers doped with impurities by ion implantation. A semiconductor device detection device according to any one of items 1 to 3. (5) The semiconductor device detection device according to any one of claims 1 to 3, wherein the separation layer is an epitaxial layer formed on the resistance layer. (6) The semiconductor device detection device according to claim 5, wherein the separation layer is a semiconductor region having a lower impurity concentration than the resistance layer. (7) The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor substrate is a silicon substrate, the resistance layer is a layer doped with boron, and the separation layer is a layer doped with phosphorus. Detection device.