JPS608629B2 - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS608629B2
JPS608629B2 JP2074976A JP2074976A JPS608629B2 JP S608629 B2 JPS608629 B2 JP S608629B2 JP 2074976 A JP2074976 A JP 2074976A JP 2074976 A JP2074976 A JP 2074976A JP S608629 B2 JPS608629 B2 JP S608629B2
Authority
JP
Japan
Prior art keywords
type
region
collector
diffusion
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP2074976A
Other languages
Japanese (ja)
Other versions
JPS52103970A (en
Inventor
和利 上林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP2074976A priority Critical patent/JPS608629B2/en
Publication of JPS52103970A publication Critical patent/JPS52103970A/en
Publication of JPS608629B2 publication Critical patent/JPS608629B2/en
Expired legal-status Critical Current

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  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置に関し、特に三重拡散型トランジ
スタを用いた集積回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to an integrated circuit using triple diffused transistors.

従来技術による三重拡散型NPNトランジスタの断面図
を図1に示す。
A cross-sectional view of a triple-diffused NPN transistor according to the prior art is shown in FIG.

P型基板1にN型領域2を形成後、各素子間のチャンネ
ル防止用P型領域3とP型ベース領域4を形成する。そ
の後N+ェミッタ領域5とN+コレクタコンタクト領域
6を作る。この従来技術の三重拡散型トランジス外こお
いては、トランジスタの飽和抵抗が通常のN十埋込み層
を有するェピタキシャル成長を行ったトランジスタに比
し2倍〜3折音〜大きくなるという非常に重大な欠点を
有している。
After forming an N-type region 2 on a P-type substrate 1, a P-type region 3 for preventing channels between each element and a P-type base region 4 are formed. Thereafter, an N+ emitter region 5 and an N+ collector contact region 6 are formed. In the case of this prior art triple diffusion type transistor, the saturation resistance of the transistor is two to three times larger than that of a transistor grown epitaxially with a normal N0 buried layer, which is extremely important. It has some drawbacks.

このため大電流の流れるトランジスタあるいは集積回路
に使用するためにはトランジスタの形状を大きくしなけ
ればならない。従って集積回路の設計製造に関し重大な
る障害となっている。また、従来技術の三重拡散型トラ
ンジスタの飽和抵抗を低下させるためには、N型コレク
タ領域2の不純物濃度をあげ横方向の抵抗を減らせばよ
いが、N型コレクタ領域2の不純物濃度をあげると、P
型ベース領域4とN型コレクタ領域2の間の逆耐圧が低
下し、製造困難となり歩蟹低下を起こす。また接合容量
も増大し、スイッチングスピードが遅くなり、トランジ
スタ、集積回路の高速性が失われるという欠点を有して
いる。本発明は上記欠点をなくし、なおかつ三重拡散型
トランジスタおよび集積回路の利点を失わない半導体装
置を提供するものである。
Therefore, in order to use it in a transistor or integrated circuit through which a large current flows, the shape of the transistor must be made large. Therefore, it has become a significant obstacle in the design and manufacture of integrated circuits. Furthermore, in order to reduce the saturation resistance of the conventional triple diffusion type transistor, it is sufficient to increase the impurity concentration of the N-type collector region 2 and reduce the lateral resistance. , P
The reverse withstand voltage between the mold base region 4 and the N-type collector region 2 is reduced, making manufacturing difficult and causing a slowdown. Further, the junction capacitance increases, the switching speed decreases, and the high-speed performance of transistors and integrated circuits is lost. The present invention provides a semiconductor device that eliminates the above-mentioned drawbacks and does not lose the advantages of triple diffused transistors and integrated circuits.

本発明の特徴はN型コレクタ領域の拡散プロフィールが
従来技術と異っていることである。
A feature of the present invention is that the diffusion profile of the N-type collector region is different from the prior art.

図2に従釆技術のN型コレクタ領域の不純物拡散プロフ
ィールを示す。図3には本発明によるN型コレクタ領域
の不純物拡散プロフィールを示す。これは表面濃度Ns
NのN型不純物拡散プロフィールを表面濃度NSpのP
型不純物拡散プロフィールで補償したもので、従来の拡
散プロフィールと異なり、実効的なN型不純物プロフィ
ールは実線の如く、表面よりある深さ入った個所に実効
最大不純物濃度を有する。即ち、N型領域の表面部分を
P型不純物で補償し表面から所望の部分だけをN−領域
にしたものである。このため、N+埋込み層を作りェピ
タキシャル成長したものと同様の特徴をもつようになり
トランジスタの飽和抵抗を小さくすることが可能となり
、なおかつトランジスタのコレクタベース間の寄生容量
の減少と逆耐圧の増大となり、トランジスタおよび集積
回路のスイッチング速度の高速性が得られ、また製造の
容易性が得られる。次に実際の製造法と実施例を図4に
示す。P型基板1(不純物濃度1ぴ4〜1び6個/塊)
にリン(P)あるいはヒ素(As)、アンチモン(Sb
)などのN型不純物を1び2〜1び6個/c確イオンィ
ンプランテーションあるいは熱拡散し(同図a)、ホウ
素(B)、ガリウム(Ga)などのP型不純物を1ぴ2
〜1び6個/水イオンィンプランテ−ションあるいは熱
拡散する(同図b)。その後熱処理を行ない、同図cの
如くなる。この時の拡散プロフィールは図3の如くなり
、実効表面濃度は1び5〜1び7個/が実効最大不純物
濃度は表面より0.5仏〜4ムで1び6〜1び8個/地
となる。N型コレクタ領域の接合深さは2〃〜15仏で
ある。その後、従来の三重拡散型と同様にチャンネル防
止用P型領域12P型ベース領域13をつくり、N+ェ
ミツタ領域14、N十コレクタコンタクー・領域15を
形成する。本発明により製造したトランジスタは飽和抵
抗を従来の三重拡散型トランジスタの飽和抵抗の10分
の1から2分の1に改善することができる。
FIG. 2 shows the impurity diffusion profile of the N-type collector region of the follower technology. FIG. 3 shows an impurity diffusion profile of an N-type collector region according to the present invention. This is the surface concentration Ns
The N-type impurity diffusion profile of N is defined as P with surface concentration NSp.
Unlike the conventional diffusion profile, the effective N-type impurity profile has an effective maximum impurity concentration at a certain depth from the surface, as shown by the solid line. That is, the surface portion of the N-type region is compensated with a P-type impurity, and only a desired portion from the surface is made into an N- region. For this reason, it has the same characteristics as those produced by forming an N+ buried layer and epitaxially growing it, making it possible to reduce the saturation resistance of the transistor, as well as reducing the parasitic capacitance between the collector and base of the transistor and increasing the reverse breakdown voltage. Therefore, high switching speeds of transistors and integrated circuits can be obtained, and ease of manufacturing can be obtained. Next, an actual manufacturing method and an example are shown in FIG. P-type substrate 1 (Impurity concentration 1 4 to 1 6 pieces/block)
Phosphorus (P) or arsenic (As), antimony (Sb)
), etc., by ion implantation or thermal diffusion (Figure a), and P-type impurities, such as boron (B), gallium (Ga), etc.
~1 to 6 pieces/water ion implantation or thermal diffusion (Figure b). After that, heat treatment is performed, and the result is as shown in FIG. The diffusion profile at this time is as shown in Figure 3, where the effective surface concentration is 1 and 5 to 1 and 7 impurities/the effective maximum impurity concentration is 0.5 to 4 mm from the surface and 1 and 6 to 1 and 8 impurities/ Become the earth. The junction depth of the N-type collector region is 2 to 15 degrees. Thereafter, as in the conventional triple diffusion type, a channel preventing P type region 12 and a P type base region 13 are formed, and an N+ emitter region 14 and an N+ collector contact region 15 are formed. Transistors manufactured according to the present invention can improve saturation resistance from one-tenth to one-half of the saturation resistance of conventional triple-diffused transistors.

更にベース・コレク夕間の逆耐圧、接合容量もェピタキ
シャル成長を行ったトランジスタと同程度にできる。本
発明を使用することにより、従来三重拡散では設計製造
不可能であった大電流を流すトランジスタ、集積回路の
設計製造を可能ならしめるものである。
Furthermore, the reverse breakdown voltage and junction capacitance between the base and collector can be made comparable to those of epitaxially grown transistors. By using the present invention, it is possible to design and manufacture transistors and integrated circuits that flow large currents, which were conventionally impossible to design and manufacture using triple diffusion.

また本発明は上記と反対導電型においても同様に適用で
きる。
Further, the present invention can be similarly applied to a conductivity type opposite to that described above.

【図面の簡単な説明】[Brief explanation of the drawing]

図1は従来技術による三重拡散型トランジスタの断面図
、図2は従来技術によるN型コレクタ領域のN型不純物
の拡散プロフィールを示す曲線図、図3は本発明による
N型コレクタ領域の実効的N型不純物の拡大プロフィー
ルを示す曲線図、図4は本発明による三重拡散型トラン
ジスタの製法と実施例を示す断面図である。 1・・・・・・P型半導体基板、2・・・・・・N型コ
レクタ領域、3・・・・・・チャンネル防止用P型領域
、4・・・・・・P型ベース領域、5・・・・・・N十
ェミッ夕領域、6・・・…N+コレクタコンタクト領域
、7・・・・・・酸化膜、8,8′・・・・・・N型領
域、9・・・・・・酸化膜、10・・・・・・酸化膜の
開孔、11・・・・・・P型不純物(N型領域を補償す
るため)、11′・・・・・・N型領域中のP型不純物
により補償された領域、12・・・・・・チャンネル防
止用P型領域、13・・・・・・P型ベース領域、14
・・・.・.N十ェミッタ領域、15・・・・・・N+
コレクタコンタクト領域。 風l 函乙 図る 図4
FIG. 1 is a cross-sectional view of a triple diffusion type transistor according to the prior art, FIG. 2 is a curve diagram showing the diffusion profile of N-type impurities in the N-type collector region according to the prior art, and FIG. FIG. 4 is a curve diagram showing an enlarged profile of type impurities, and FIG. 4 is a cross-sectional view showing a manufacturing method and an embodiment of a triple diffusion type transistor according to the present invention. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type collector region, 3... P-type region for channel prevention, 4... P-type base region, 5...N10 emitter region, 6...N+ collector contact region, 7...Oxide film, 8, 8'...N type region, 9... ...Oxide film, 10...Open hole in oxide film, 11...P-type impurity (to compensate for N-type region), 11'...N-type Region compensated by P-type impurity in the region, 12... P-type region for channel prevention, 13... P-type base region, 14
....・.. N ten emitter regions, 15...N+
Collector contact area. Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1 三重拡散型トランジスタを含む半導体装置において
、コレタク領域のコレクタ接合に近接する部分がコレク
タ領域の他の部分に比較して高比抵抗となっていること
を特徴とする半導体装置。
1. A semiconductor device including a triple diffused transistor, characterized in that a portion of a collector region close to a collector junction has a higher specific resistance than other portions of the collector region.
JP2074976A 1976-02-26 1976-02-26 semiconductor equipment Expired JPS608629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2074976A JPS608629B2 (en) 1976-02-26 1976-02-26 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2074976A JPS608629B2 (en) 1976-02-26 1976-02-26 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS52103970A JPS52103970A (en) 1977-08-31
JPS608629B2 true JPS608629B2 (en) 1985-03-04

Family

ID=12035826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2074976A Expired JPS608629B2 (en) 1976-02-26 1976-02-26 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS608629B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540615Y2 (en) * 1988-04-01 1993-10-14

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62262459A (en) * 1986-05-09 1987-11-14 Fujitsu Ltd Manufacture of semiconductor device
JPH01194364A (en) * 1988-01-28 1989-08-04 Nec Corp Longitudinal type high dielectric strength semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0540615Y2 (en) * 1988-04-01 1993-10-14

Also Published As

Publication number Publication date
JPS52103970A (en) 1977-08-31

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