JPH0110938Y2 - - Google Patents
Info
- Publication number
- JPH0110938Y2 JPH0110938Y2 JP16568481U JP16568481U JPH0110938Y2 JP H0110938 Y2 JPH0110938 Y2 JP H0110938Y2 JP 16568481 U JP16568481 U JP 16568481U JP 16568481 U JP16568481 U JP 16568481U JP H0110938 Y2 JPH0110938 Y2 JP H0110938Y2
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- diode
- base
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009792 diffusion process Methods 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 108091006146 Channels Proteins 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【考案の詳細な説明】
本考案はコレクタにダイオードが順方向に接続
されたスイツチング用トランジスタの構造に関
し、特に寄生サイリスタ効果の防止及びスイツチ
ング特性の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a switching transistor in which a diode is forwardly connected to the collector, and in particular to prevention of parasitic thyristor effects and improvement of switching characteristics.
一般にスイツチング用トランジスタの中には逆
サージ電圧吸収用のダイオードがコレクタに接続
されて一つのチツプ内に形成されたものがある。 Generally, some switching transistors have a diode for absorbing reverse surge voltage connected to the collector and formed within one chip.
第1図は従来のダイオード内蔵型スイツチング
トランジスタの構造を示す断面図であり、1はリ
ン等の不純物が高濃度に拡散されたN+型の半導
体基体であり、半導体基体1上にはコレクタ領域
となるN−型のエピタキシヤル層2が形成され
る。またエピタキシヤル層2にはボロン等の不純
物の拡散に依つて逆導電型、即ちP型のベース領
域3及びダイオード領域4が形成され、更にベー
ス領域3内にはリン等の不純物の高濃度拡散に依
つてN+型のエミツタ領域5が形成され、各領域
にアルミニウムのオーミツク接触に依つて電極
6,7,8が形成されている。 FIG. 1 is a cross-sectional view showing the structure of a conventional switching transistor with a built-in diode. Reference numeral 1 denotes an N+ type semiconductor substrate in which impurities such as phosphorus are diffused at a high concentration, and a collector region is formed on the semiconductor substrate 1. An N-type epitaxial layer 2 is formed. Further, in the epitaxial layer 2, a base region 3 and a diode region 4 of opposite conductivity type, that is, P type, are formed by diffusion of impurities such as boron, and furthermore, in the base region 3, impurities such as phosphorus are diffused at a high concentration. An N+ type emitter region 5 is formed by the wafer, and electrodes 6, 7, 8 are formed in each region by ohmic contact with aluminum.
上述の構造は第2図aの回路で示され、ベース
電流が流れることに依つてダイオード9を介して
コレクタ電流が流れる逆サージ電圧が生じた場合
にはダイオード9の逆方向耐圧に依つて吸収され
外部回路への逆サージ電圧の印加がなくなるので
ある。しかし、第1図に示された構造に依ると第
2図bに示される如く、ダイオード領域4をエミ
ツタ、エピタキシヤル層2をベース、及びベース
領域3をコレクタとする様な寄生トランジスタ1
0が形成され、パルス状の高電圧等が印加された
場合、サイリスタ動作、即ちベース電流が取り除
かれたときでも、寄生トランジスタ10のコレク
タからベース電流が供給されて、トランジスタ1
1の遮断が為されなくなる動作が生じ、スイツチ
ングトランジスタとしての動作が不能となる欠点
を有していた。 The above structure is shown in the circuit of FIG. 2a, and when a reverse surge voltage occurs, in which the collector current flows through the diode 9 due to the base current flowing, it is absorbed by the reverse withstand voltage of the diode 9. This eliminates the application of reverse surge voltage to the external circuit. However, according to the structure shown in FIG. 1, as shown in FIG. 2b, a parasitic transistor 1 is formed in which the diode region 4 is the emitter, the epitaxial layer 2 is the base, and the base region 3 is the collector.
0 is formed and a pulse-like high voltage is applied, the thyristor operates, that is, even when the base current is removed, the base current is supplied from the collector of the parasitic transistor 10, and the transistor 1
This has the drawback that the switching transistor cannot function as a switching transistor.
本考案は上述した点に鑑みて為されたものであ
り、従来の欠点を完全に除去したスイツチング用
トランジスタを提供するものである。以下図面を
参照して本考案を詳述する。 The present invention has been devised in view of the above-mentioned points, and is intended to provide a switching transistor that completely eliminates the conventional drawbacks. The present invention will be described in detail below with reference to the drawings.
第3図は本考案の実施例を示す断面図であり、
12はシリコンから成り、リン等の不純物が高濃
度に拡散されたN+型の半導体基体であり、半導
体基体12上には気相成長法等に依りリン等の不
純物が低濃度に拡散され、コレクタ領域となるN
−型のエピタキシヤル層13が形成される。エピ
タキシヤル層13にはその表面からボロン等の不
純物が拡散されP型のベース領域14及びダイオ
ード領域15とが同時に形成され、またベース領
域14内にはリン等の不純物が高濃度に拡散され
N+型のエミツタ領域16が形成される。 FIG. 3 is a sectional view showing an embodiment of the present invention,
Reference numeral 12 denotes an N+ type semiconductor substrate made of silicon, in which impurities such as phosphorus are diffused at a high concentration. On the semiconductor substrate 12, impurities such as phosphorus are diffused at a low concentration by vapor phase growth, etc., and a collector is formed. N becomes the area
- type epitaxial layer 13 is formed. An impurity such as boron is diffused into the epitaxial layer 13 from its surface to simultaneously form a P-type base region 14 and a diode region 15, and an impurity such as phosphorus is diffused into the base region 14 at a high concentration to form an N+ A mold emitter region 16 is formed.
一方ベース領域14とダイオード領域15の間
には両者を分離するためのN+埋込層17がエミ
ツタ領域16の形成と同時に形成されている。N
+埋込層17はエピタキシヤル層13表面に誘起
されるチヤンネルを阻止し、ベース領域14とダ
イオード領域15が導通するのを防止している。
本考案の特徴はこのN+埋込層17を中心にして
金属拡散層18を形成する点にある。金属拡散層
18はエミツタ領域16及びN+埋込層17の形
成後N+埋込層17上の酸化膜を除去し、金ある
いは白金等をその表面に付着せしめ、拡散炉に於
いて約1100℃程度に加熱処理することに依り、N
+埋込層17を中心にエピタキシヤル層13内部
半導体基板12に達するまで拡散し形成される。 On the other hand, an N+ buried layer 17 is formed between the base region 14 and the diode region 15 to separate the two at the same time as the emitter region 16 is formed. N
The buried layer 17 blocks a channel induced on the surface of the epitaxial layer 13 and prevents the base region 14 and the diode region 15 from being electrically connected.
The feature of the present invention is that a metal diffusion layer 18 is formed around this N+ buried layer 17. After forming the emitter region 16 and the N+ buried layer 17, the metal diffusion layer 18 is formed by removing the oxide film on the N+ buried layer 17, depositing gold or platinum, etc. on its surface, and heating it in a diffusion furnace at about 1100°C. By heat treatment, N
+ It is formed by diffusing around the buried layer 17 until it reaches the semiconductor substrate 12 inside the epitaxial layer 13.
電極19,20,21はエピタキシヤル層13
上を被覆している酸化膜22のベース領域14、
エミツタ領域16及びダイオード領域15上の一
部を除去し、アルミニウムのオーミツク接触に依
り形成される。 Electrodes 19, 20, 21 are epitaxial layer 13
a base region 14 of an overlying oxide film 22;
A portion of the emitter region 16 and diode region 15 is removed and an ohmic contact made of aluminum is formed.
上述の構造に依ればエミツタ領域16から注入
されエピタキシヤル層13内を移動するキヤリア
のライフタイムは金属拡散層18に於ける再結合
で短くなり、ベース電流IBの遮断とコレクタ電流
の遮断との時間的ずれが小さくなる。またエピタ
キシヤル層13をベース領域とする寄生トランジ
スタに於いてはダイオード領域15から注入され
るキヤリアは金属拡散層18中で再結合してしま
うためトランジスタとしての動作をしなくなり、
スイツチングトランジスタへのベース電流の供給
が阻止され、所謂サイリスタ動作が防止されるの
である。更に従来のスイツチングトランジスタの
特性が第4図aであつたとすると、コレクタ領
域、即ちエピタキシヤル領域13内に金属拡散層
18を設けることに依つてコレクタ抵抗が減少
し、第4図bに示す如く同一のベース電流IBに依
つてより大きなコレクタ電流を流すことができる
ものである。 According to the above structure, the lifetime of carriers injected from the emitter region 16 and moving in the epitaxial layer 13 is shortened by recombination in the metal diffusion layer 18, and the base current I B and the collector current are blocked. The time difference between Furthermore, in a parasitic transistor having the epitaxial layer 13 as a base region, carriers injected from the diode region 15 recombine in the metal diffusion layer 18, so that it no longer operates as a transistor.
The supply of base current to the switching transistor is blocked, and so-called thyristor operation is prevented. Furthermore, assuming that the characteristics of the conventional switching transistor are as shown in FIG. 4a, the collector resistance is reduced by providing the metal diffusion layer 18 in the collector region, that is, the epitaxial region 13, as shown in FIG. 4b. Thus, a larger collector current can be caused to flow with the same base current I B .
従つて本考案に依ればベース領域とダイオード
領域との間のコレクタ領域内に金属拡散層を形成
することに依り、寄生サイリスタ効果を防止でき
ると共にスイツチング特性をも向上させることが
できる実用的効果大なるものである。 Therefore, according to the present invention, by forming a metal diffusion layer in the collector region between the base region and the diode region, the parasitic thyristor effect can be prevented and the switching characteristics can also be improved. It is a big thing.
第1図は従来例を示す断面図、第2図a,bは
第1図に示された半導体装置の等価回路、第3図
は本考案の実施例を示す断面図、第4図a,bは
従来と本考案に於けるトランジスタの特性図であ
る。
12……半導体基体、13……エピタキシヤル
層、14……ベース領域、15……ダイオード領
域、16……エミツタ領域、17……N+埋込
層、18……金属拡散層、19,20,21……
電極、22……酸化膜。
FIG. 1 is a sectional view showing a conventional example, FIGS. 2a and 2b are equivalent circuits of the semiconductor device shown in FIG. 1, FIG. 3 is a sectional view showing an embodiment of the present invention, and FIGS. b is a characteristic diagram of transistors in the conventional and the present invention. 12...Semiconductor substrate, 13...Epitaxial layer, 14...Base region, 15...Diode region, 16...Emitter region, 17...N+ buried layer, 18...Metal diffusion layer, 19, 20, 21...
Electrode, 22... oxide film.
Claims (1)
コレクタ領域内に逆導電型の不純物の拡散に依つ
て形成されたベース領域と、該ベース領域内に前
記半導体基板と同導電型の不純物の拡散に依つて
形成されたエミツタ領域と、前記コレクタ領域内
に逆導電型の不純物の拡散に依つて形成されたダ
イオード領域とを備えた半導体装置に於いて、前
記ベース領域と前記ダイオード領域の間のコレク
タ領域内に前記半導体基体と同導電型の高濃度不
純物層と、該高濃度不純物層を中心として金属拡
散層とが形成されることを特徴とする半導体装
置。 a collector region formed on a semiconductor substrate; a base region formed in the collector region by diffusion of impurities of opposite conductivity type; and a base region formed by diffusion of impurities of the same conductivity type as the semiconductor substrate in the base region. and a diode region formed by diffusing impurities of opposite conductivity type into the collector region, the collector region between the base region and the diode region is provided. A semiconductor device characterized in that a high concentration impurity layer of the same conductivity type as the semiconductor substrate and a metal diffusion layer are formed around the high concentration impurity layer in a region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16568481U JPS5869942U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16568481U JPS5869942U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5869942U JPS5869942U (en) | 1983-05-12 |
JPH0110938Y2 true JPH0110938Y2 (en) | 1989-03-29 |
Family
ID=29957873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16568481U Granted JPS5869942U (en) | 1981-11-05 | 1981-11-05 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5869942U (en) |
-
1981
- 1981-11-05 JP JP16568481U patent/JPS5869942U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5869942U (en) | 1983-05-12 |
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