JPS58197760A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make the resistance value of the titled semiconductor device variable using the voltage applied on an N-layer by a method wherein a small-sized resistor device is formed on the layer located in the deep section by providing the N-layer on the surface of a P<-> layer. CONSTITUTION:The P<-> layer 1 is provided as a resistance layer, and then an N<+> layer 9 is formed thereon. When the substrate potential is VDD and a positive voltage is applied to an electrode 10, the layers 1 and 8 are biased inversely and a depletion layer is spread out on the side of the P<-> layer 1, thereby enabling to increase the resistance value between input and output terminals 4 and 5. Also, when the substrate potential is formed in variable structure, the upper and lower junctions of P<-> resistance are controlled simultaneously by connecting the N<+> layer 9 located at the upper part of the P<-> resistance layer and by using the electrode 10 as a control electrode, thereby enabling to control the resistance value in a wider range.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is a monolithic, integrated circuit (
The present invention relates to a resistor device that is compact and has a structure that allows variable resistance in integrated circuits (hereinafter simply referred to as integrated circuits).

FIG. 1 shows an example of a resistor device of a complementary field effect transistor integrated circuit (hereinafter referred to as a CMO8 integrated circuit) formed on an N-type substrate. When forming a resistor in a CMO8 integrated circuit, a P-type diffusion layer or an N-type diffusion layer is usually used, but if a high resistance is required, the resistance length f
In order to reduce the size of the resistor layer, P-type low concentration No. 1, which has a high p-resistivity, is used as the resistance layer. However, it is still several tens of Ω
If the resistor is larger, it will occupy a large area on the integrated circuit.

Therefore, in the present invention, N is added to the surface layer of the P-type low concentration layer.
It is recommended to provide a type diffusion layer and use it as an exploration layer urban resistance layer for the P-type low concentration layer! This is achieved by reducing the size of the tube and at the same time making the resistance variable by applying a voltage to the Nfi diffusion layer in one surface layer.This will be explained in detail below with reference to the drawings.

FIG. 2 shows an implementation machine of the present invention, in which 1 is a P″″ resistance layer, 2
is the P+ diffusion layer, 3 is the N+ guard ring, 4°5 is the exposed AI wiring, 6 is the field oxide film, 7 is the N--11i board, 8 is the bottom layer, 9 is the N+ layer, lo#-i resistor This is a control electrode. In order to increase the effect of N of 8 and N+# of Fi9, the resistance value of the P-resistance layer 1 is increased, and the withstand voltage between the P-resistance layer 1 is increased.

By applying a positive voltage to the electrode 10, the P-low concentration layer 1 and the N-layer 8 are reverse biased. At this time, when the total applied voltage increases, the depletion layer of the reverse biased junction becomes P-
Because it spreads to the low concentration layer side, as a result, input/output terminals 4 and 5
The resistance value between them will increase.

The second diagram shows 0M08 where the substrate potential is fixed at ■DD potential.
As an example of an integrated circuit, if the circuit has a structure (isolation structure) in which the substrate potential can be changed, the structure shown in diagram #I3 is possible. N+ diffusion layer 9 above P- resistance layer 1
By making the and guard ring 3 continuous and using 10 as a control electrode, the upper and lower junctions of the P-resistance layer can be controlled simultaneously, making it possible to control the resistance value over a wider range.

As explained above, in the present invention, the P-type low concentration layer 1
By forming one resistive layer on top of the resistive layer and forming an N-type diffusion layer 8.9 on top of the resistive layer, the resistive device could be made smaller, and the resistance value could be made variable by changing the voltage applied to the ten electrodes. Further, even when there is no need to make the resistance variable, a resistance value greater than pl can be obtained by biasing the 10 electrodes to a positive potential, and as a result, the device can be further miniaturized.

In the #-structured embodiment of the present invention shown in FIG.
, 10 Cm, 5 x 10"cm-", the resistance value was 15 to 0 when the control voltage was 0, and the resistance change rate with respect to the control voltage was 2.2 to Ω/. .

[Brief explanation of drawings]

The first factor is the conventional resistance j1! A sectional view (G), tjIX2, and 3 of the plane of Narita, taken along line 11 of the plan view, are a plan view and a sectional view of an embodiment of the present invention. Furthermore, in -

Claims (1)

[Claims] In a resistance device formed of a diffusion layer of a conductivity type opposite to that of a semiconductor substrate and a diffusion layer of the same conductivity type as the substrate in the surface layer portion of the diffusion layer, the resistance at is variable depending on the potential of the substrate or the surface diffusion layer. A semiconductor device exhibiting tS characteristics.