JPS63237474A - Integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an integrated circuit with high integration density, by forming a buried resistor in the inside of a single epitaxial layer, and forming a bipolar transistor and a junction capacitor on the surface. CONSTITUTION:In a single epitaxial layer 2 surrounded by an isolation region 4, the following are formed: a transistor, a buried resistor 3 of an N<-> type diffusion layer formed so as to bridge a P-type silicon substrate 1 and the epitaxial layer 2, and a junction capacitor CT of a P<+> region 8p forming a junction part together with an N<+> region 8n being the upper layer of the epitaxial layer 2. The long side l and the short side w are, for example, 440mum and 85mum, respectively, and the occupied area is reduced to 35,400mum<2> which corresponds to about 40% of the usual area. Although the equivalent internal resistance of a collector increases as compared with the usual one, it has no objection to small power application of high frequency.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to integrated circuits.

[Conventional technology]

As integrated circuits become more highly integrated, the area occupied by internal resistance elements and capacitor elements has become a problem.

[Conventional technology]

-m, there are three types of integration circuits that can be applied to about 100MH2: bipolar transistors, resistors, and capacitors.
The elements are configured within the same integrated circuit.

FIGS. 3(a) and 3(b) are a schematic cross-sectional view and a plan view excluding the oxide film and each electrode of an example of a conventional integrated circuit.

Each element formation region is formed by selectively introducing n+ type impurities into the surface of a p-type silicon substrate 1, and then growing an n- type epitaxial layer 2 over the entire surface of the silicon substrate 1. It is surrounded by a p+ isolation region 4 reaching .

In this case, the n+ type impurity is also diffused into the epitaxial layer 2 of the silicon substrate 1 to form a buried N13 having a resistivity lower than that of the epitaxial layer 2, and the equivalent internal resistance of the collector region 7 is reduced to rO and rl. lower to the parallel value of .

The bipolar transistor includes a p+ base region 5 formed by selective diffusion in the upper layer of the epitaxial layer above the buried layer 13, an n+ emitter region 6 provided in a part of the upper layer, and the remaining epitaxial layer 2. and a collector area 7.

The resistor 11 is formed as a p+ type diffusion layer at the same time as the base region 5 in the upper layer of the epitaxial layer 2 in the same element formation region as the bipolar transistor.

The capacitor C is constructed by forming an n+ region 12n on the upper layer of other element formation regions by selective diffusion similar to the emitter region 6, and then further Ae on the surface of the silicon oxide film 9 covering the surface.
It is composed of an electrode 12a.

As shown in FIG. 3(b), the long side and short side W of the two epitaxial layers 2 constituting the integrating circuit are, for example, 780 μm and 110 μm, respectively, and the area occupied by the three integrating circuit elements is approximately 85,800 μm2. Become.

FIG. 4 is an equivalent circuit diagram of the integrated circuit of FIG. 3.

As shown by the dotted line, the emitter electrode T6 and the Ae electrode T12
．． An emic ground circuit is constructed by connecting the collector electrode T7 and the resistor electrode T11a, and the resistor electrode Tl1b and the capacitor electrode T12 through wiring layers, respectively.

The power supply voltage V is applied to the collector electrode T7 via the load resistor RL.

When given, the base input signal Vt becomes an integral waveform whose specific number is the product of the value of the equivalent resistance R and the value of the capacitor C shown by the dotted line, and an output signal Vo is obtained at the terminal TIH.

As an example, when the operating frequency is 50 to 100 MHz, the value of the resistor R is 100 to 500Ω, and the value of the capacitor C is about 10 pF.

[Problem that the invention seeks to solve]

The above-described conventional integrated circuit requires a planar area for three elements, a bipolar transistor, a resistor, and a capacitor, as an integrating circuit, and therefore has a problem in that it cannot be highly integrated.

An object of the present invention is to provide a highly integrated circuit.

[Means for solving problems]

The integrated circuit device of the present invention includes: (A) an inverse structure formed on one principal surface of a silicon substrate of one conductivity type, divided into a plurality of element formation regions by a separation region of one conductivity type reaching from the surface to the silicon substrate; an epitaxial layer of a conductivity type, (B) a base region of one conductivity type selectively formed in the upper layer of the epitaxial layer, an emitter region of the opposite conductivity type formed in the upper layer of the base region, and a bipolar transistor having a collector region; (C) a buried resistor of an opposite conductivity type selectively formed across the silicon substrate and the collector region; (D) selectively formed in an upper layer of the epitaxial layer; A region of one conductivity type with a higher concentration than the epitaxial layer provided from the epitaxial layer to the one of the two conductivity regions is used as the other electrode layer. It is configured to include a junction capacitor whose capacitance is a junction between the opposite conductivity type region and the one conductivity type region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a schematic cross-sectional view and a plan view excluding the oxide film and each electrode of an embodiment of the present invention.

In a single epitaxial layer 2 surrounded by an isolation region 4,
A transistor, a buried resistor 3 made of an n-swelled diffusion layer provided across the p-type silicon substrate 1 and the epitaxial layer 2, and an n+ region 8 on the upper layer of the epitaxial layer 2.
A junction capacitor CA is provided with a p+ region 82 forming a junction with n.

Here, the base region 5 and emitter region 6 of the bipolar transistor are the same as the conventional one shown in FIG.

As shown in FIG. 1(b), the long side l and short side W of the epitaxial layer 2 are, for example, 440/i m and 85 μm, respectively.
m, and the occupied area is about 4 times the conventional area shown in Figure 3 above.
0% reduction to 35,400 m2.

The impurity concentration of the buried resistor 3 is n-, and the buried resistor 3 has an impurity concentration of n-.
It is thinner than the impurity concentration n+ of collector region 7 and higher than the impurity concentration of collector region 7. Therefore, the resistance value r2 of the embedded resistor 3 is smaller than the parallel collector resistance r.

Although the equal-side internal resistance of the collector is increased compared to the conventional one, there is no problem in high-frequency, low-power applications.

FIG. 2 is an equivalent circuit of the integrated circuit of FIG.

As shown by the dotted line, the emitter terminal T6 and the terminal T8n of the n+ region 8n are connected in the wiring layer to form an emitter grounded circuit, and the power supply voltage V is connected to the collector terminal T7 via the load resistor RL.
When C is given, the input signal Vi becomes an integral waveform with the value of the equivalent resistance RT shown by the dotted line and the value of the capacitor CT as specific numbers,
Output signal VO is obtained from terminal T1o.

〔Effect of the invention〕

As explained above, the present invention has the effect that a highly integrated circuit can be obtained by forming an embedded resistor inside a single epitaxial layer and a bipolar transistor and a junction capacitance on the surface. .

[Brief explanation of drawings]

1(a) and 1(b) are schematic cross-sectional views of one embodiment of the present invention and a cross-sectional view excluding the oxide film and each electrode, and FIG. 2 is a schematic sectional view of one embodiment of the present invention.
3(a) and 3(b) are a schematic cross-sectional view and a plan view of an example of a conventional integrated circuit and a plan view excluding the arsenic film and each electrode. 3 is an equivalent circuit diagram of the integrated circuit of FIG. 3. 1... Silicon substrate, 2... Epitaxial layer, 3
. . . Embedded resistor, 4. Isolation region, 5. Base region, 6. Emitter region, 7. Collector region.
8n...n'' region, 8p...p1 region, 11...
Resistor, CT...junction capacitor.

Claims (1)

[Scope of Claims] (A) An opposite conductivity type formed on one main surface of a silicon substrate of one conductivity type, divided into a plurality of element formation regions by a separation region of one conductivity type reaching from the surface to the silicon substrate. (B) a base region of one conductivity type selectively formed in the upper layer of the epitaxial layer, an emitter region of the opposite conductivity type formed in the upper layer of the base region, and a collector composed of the epitaxial layer; (C) a buried resistor of an opposite conductivity type selectively formed across the silicon substrate and the collector region; (D) a bipolar transistor selectively formed in an upper layer of the epitaxial layer; A region of one conductivity type is used as one electrode layer, and a region of the opposite conductivity type, which is provided from the epitaxial layer to the one conductivity type region and has a higher concentration than the epitaxial layer, is used as the other electrode layer. An integrated circuit comprising: a junction capacitor whose capacitance is a junction between the opposite conductivity type region and the one conductivity type region.