JPS61102766A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS61102766A JPS61102766A JP59226299A JP22629984A JPS61102766A JP S61102766 A JPS61102766 A JP S61102766A JP 59226299 A JP59226299 A JP 59226299A JP 22629984 A JP22629984 A JP 22629984A JP S61102766 A JPS61102766 A JP S61102766A
- Authority
- JP
- Japan
- Prior art keywords
- input
- surge voltage
- internal circuit
- semiconductor integrated
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000003990 capacitor Substances 0.000 abstract description 6
- 230000002238 attenuated effect Effects 0.000 abstract description 4
- 239000011810 insulating material Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ラッチアップ耐圧の高いチンプレイアウト
を持つ半導体集積回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit having a chiin layout with high latch-up resistance.
第３図は従来の半導体集積回路を示し、図において、１
．２はそれぞれＶＤＤ及び■ｓｓライン（電源ライン）
、３は内部回路の一部を示す。FIG. 3 shows a conventional semiconductor integrated circuit, in which 1
．． 2 are VDD and ■ss line (power supply line) respectively
, 3 shows a part of the internal circuit.
半導体集積回路の動作時、電源ラインにサージ電圧が加
わると、それが該内部回路まで伝播され、ランチアンプ
を起こす原因となっている。従来の半導体集積回路のチ
ンプレイアウトは第３図に示す通り、電源ラインから直
接核内部回路３に電源が供給されている。よって、電源
ラインにサージ電圧が加わった場合、上述の如く、サー
ジ電圧によるラッチアップが起こ葛可能性があるが、本
従来回路にはそれに対する防止策は何ら施されていない
。When a surge voltage is applied to a power supply line during operation of a semiconductor integrated circuit, it is propagated to the internal circuit, causing a launch amplifier to occur. As shown in FIG. 3, in the chip layout of a conventional semiconductor integrated circuit, power is supplied directly to the core internal circuit 3 from the power supply line. Therefore, when a surge voltage is applied to the power supply line, latch-up due to the surge voltage may occur as described above, but this conventional circuit does not take any measures to prevent this.
従来の半導体集積回路は以上のように構成されており、
サージ電圧に対する対策が全（施されておらず、電源ラ
インにサージが加わると該内部回路にまでサージ電圧が
加わり、それが原因でランチアンプが引き起こされると
いう問題点があった。Conventional semiconductor integrated circuits are configured as described above.
There was a problem in that no measures were taken against surge voltages, and when a surge was applied to the power supply line, the surge voltage was applied to the internal circuit, which caused the launch amplifier to be activated.
この発明は、上記のような問題点を解消するためになさ
れたもので、電源ラインに加わったサージ電圧によりラ
フチアツブが引き起こされるのを防止できる半導体集積
回路を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit that can prevent rough swelling caused by surge voltage applied to a power supply line.
この発明に係る半導体集積回路は、内部回路に電源を供
給するための電源ラインと該内部回路との間にサージを
減衰するための入出力素子を設けたものである。A semiconductor integrated circuit according to the present invention is provided with an input/output element for attenuating surges between a power supply line for supplying power to an internal circuit and the internal circuit.
この発明においては、電源ラインに加わったサージ電圧
は入出力素子により減衰されるから、急峻な電圧が鈍（
なり、ランチアップが防止される。In this invention, the surge voltage applied to the power supply line is attenuated by the input/output element, so that a steep voltage becomes dull (
This prevents lunch-up.
以下、この発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による半導体集積回路を示し
、図゛において、ｌはＶＤロライン、２は■ＳＳライン
、３は内部回路の一部、４は号−ジ減衰用の入出力素子
である。第１図に示すように、■ロ０ラインｌ及び■Ｓ
Ｓライン２は入出力素子４を介して該内部回路３に接続
されている。FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. It is element. As shown in Figure 1, ■Ro 0 line l and ■S
The S line 2 is connected to the internal circuit 3 via an input/output element 4.
ま□た第２図は第１図の入出力素子の断面構造を示し、
図において、５．６はＰＮ接合部、７はゲート、８はゲ
ート電極、９はドレイン電極、１０は酸化膜である。Also, Figure 2 shows the cross-sectional structure of the input/output element in Figure 1,
In the figure, 5.6 is a PN junction, 7 is a gate, 8 is a gate electrode, 9 is a drain electrode, and 10 is an oxide film.
次に第１，２図を用いて作用について説明する。Next, the operation will be explained using FIGS. 1 and 2.
本実施例装置では以上のように、該内部回路３に直接電
源を供給せず入出力素子４を介して供給するようにして
おり、これにより、例えば■ＳＳライン２に正のサージ
電圧が加わった場合、そのサージ電圧は第２図における
入出力素子を構成するＰＮ接合部５にかかる。この時、
接合付近の電子と正孔はそれぞれ分離されて高抵抗の絶
縁物に近い層、即ち空乏層ができ、電圧はこの空乏層に
かかる。このように絶°縁物をはさんで電圧がかかっ４
ている状態はコンデンサと等価である。よって急峻なサ
ージ電圧はこのＰＮ接合部にできたコンデンサに電荷を
チャージアンプする分、鈍ったものになる。As described above, in the device of this embodiment, power is not directly supplied to the internal circuit 3, but is supplied via the input/output element 4. As a result, for example, a positive surge voltage is applied to the SS line 2. In this case, the surge voltage is applied to the PN junction 5 forming the input/output element in FIG. At this time,
Electrons and holes near the junction are separated, creating a high-resistance layer similar to an insulator, that is, a depletion layer, and a voltage is applied to this depletion layer. In this way, voltage is applied across the insulating material.
This state is equivalent to that of a capacitor. Therefore, the steep surge voltage becomes dull due to the charge amplification of the charge in the capacitor formed at this PN junction.
また、第２図において、ＰＮ接合部６はダイオードであ
り、ＶＤＤライン１に正のサージ電圧が加わるとこのダ
イオードにサージがかかり、これに順方向電圧が印加さ
れた状態となるので、このＰＮ接合部においては電子及
び正孔が各々相手方へ流れこみ、電流が発生することに
なる。よって、電源ラインに加わったサージ電圧は、上
記ダイオードのオン抵抗により、急峻な電圧が鈍ったも
のになる。In addition, in FIG. 2, the PN junction 6 is a diode, and when a positive surge voltage is applied to the VDD line 1, a surge is applied to this diode, and a forward voltage is applied to it. At the junction, electrons and holes each flow into the other, generating a current. Therefore, the surge voltage applied to the power supply line becomes a voltage that is steep due to the on-resistance of the diode.
上述したようなコンデンサ及びダイオードは、入出力素
子毎に存在するから、第１図に示すように、ＶＤＤライ
ン及び■ＳＳラインを該内部回路に至るまでに複数個の
直列の入出力素子を介して接続されるようにレイアウト
すれば、複数のコンデンサ及びダイオードによる、サー
ジ電圧の大幅な減衰効果を期待できる。The capacitors and diodes mentioned above exist for each input/output element, so as shown in Figure 1, the VDD line and ■SS line must be routed through multiple series input/output elements to reach the internal circuit. If the layout is such that multiple capacitors and diodes are connected, a significant surge voltage attenuation effect can be expected.
なお、上記実施例では、半導体集積回路の基板にＰ型の
ものを使用した場合について説明したが、Ｎ型基板であ
ってもよく、上記実施例と同様の効果を奏する。In the above embodiment, the case where a P-type substrate is used as the substrate of the semiconductor integrated circuit has been described, but an N-type substrate may be used, and the same effects as in the above embodiment can be obtained.
以上のように、この発明によれば、電源ラインを入出力
素子を介して内部回路に接続するようにしたので、Ｍｉ
ｌｌラインに加わったサージ電圧は入出力素子によって
減衰され、内部回路のランチアップが防止される効果が
ある。As described above, according to the present invention, since the power supply line is connected to the internal circuit via the input/output element, the Mi
The surge voltage applied to the ll line is attenuated by the input/output elements, which has the effect of preventing launch-up of the internal circuit.
第１図はこの発明の一実施例による半導体Ｓ積回路の電
源ラインのレイアウトを示す図、第２図はこの発明の一
実施例による半導体集積回路の入出力素子の断面構造を
示す図、第３図は従来の半導体集積回路の電源ラインの
レイアウトを示す図である。
図において、ｌはＶＤＤライン、２は■ＳＳライン、３
は内部回路、４は入出力素子、５．６はＰＮ接合部、７
はゲート、８はゲート電極、９はドレイン電極、１０は
酸化膜である。
なお図中同一符号は同−又は相当部分を示す。1 is a diagram showing the layout of a power supply line of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a cross-sectional structure of an input/output element of a semiconductor integrated circuit according to an embodiment of the present invention FIG. 3 is a diagram showing the layout of power supply lines of a conventional semiconductor integrated circuit. In the figure, l is the VDD line, 2 is the SS line, and 3
is the internal circuit, 4 is the input/output element, 5.6 is the PN junction, 7
8 is a gate electrode, 9 is a drain electrode, and 10 is an oxide film. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
該電源ラインと上記内部回路との間にサージ減衰用の入
出力素子を挿入接続したことを特徴とする半導体集積回
路。(1) A power line for supplying power to the internal circuit,
A semiconductor integrated circuit characterized in that an input/output element for surge attenuation is inserted and connected between the power supply line and the internal circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59226299A JPS61102766A (en) | 1984-10-26 | 1984-10-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59226299A JPS61102766A (en) | 1984-10-26 | 1984-10-26 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61102766A true JPS61102766A (en) | 1986-05-21 |
Family
ID=16843033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59226299A Pending JPS61102766A (en) | 1984-10-26 | 1984-10-26 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61102766A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0276850A2 (en) * | 1987-01-28 | 1988-08-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
| JPH05129529A (en) * | 1991-10-31 | 1993-05-25 | Nec Corp | Semiconductor input protective device |
| EP1024538A1 (en) * | 1999-01-29 | 2000-08-02 | STMicroelectronics S.r.l. | MOS varactor, in particular for radio-frequency transceivers |
-
1984
- 1984-10-26 JP JP59226299A patent/JPS61102766A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0276850A2 (en) * | 1987-01-28 | 1988-08-03 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with latch up preventing structure |
| JPH05129529A (en) * | 1991-10-31 | 1993-05-25 | Nec Corp | Semiconductor input protective device |
| EP1024538A1 (en) * | 1999-01-29 | 2000-08-02 | STMicroelectronics S.r.l. | MOS varactor, in particular for radio-frequency transceivers |
| US6400001B1 (en) | 1999-01-29 | 2002-06-04 | Stmicroelectronics S.R.L. | Varactor, in particular for radio-frequency transceivers |
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