JPH0360152A - Input protecting circuit for semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of latchup by forming a first conductivity type semiconductor layer on the junction surface side facing a first conductivity type high concentration diffusion layer, in a second conductivity type semiconductor layer, and connecting a semiconductor device with an output terminal. CONSTITUTION:An N<+> diffusion layer 30 is formed on the one side end portion of the main surface of an N-type substrate 1, and a P-type semiconductor layer 31 is formed on the layer 30 by selective epitaxial method or the like. On the junction surface side facing the N<+> diffusion layer 30, in the P-type semiconductor layer 31, an N-type semiconductor layer 31A is formed by diffusing upward N-type impurity in the N<+> diffusion layer 30. A resistor 34 is formed by using a P-type semiconductor layer 31. The one end of the resistor 34 is connected with an input terminal 14 side. A first diode 35 is formed by a PN junction of the P-type semiconductor layer 31 forming the resistor 34 and the N-type semiconductor layer 31A. The cathode of said diode is connected with a power supply VDD via an N<+> type substrate contact region 3.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to an input protection circuit for a semiconductor device.

(Prior Art) Conventionally, as a circuit for this scale, the circuit shown in FIG. 6 is known (see Tokukai No. 62-259595).

In the figure, 1 is an N-type substrate, and the main surface of the N-type substrate 1 has a P+ diffusion layer 2. N4 board contact! A region 3 and two P wells 4 and 5 are formed, and a P1 well contact region 6 is formed at one end of the surface of the P well 4. Further, an N1 diffusion layer 7 for a diode is formed in the P well 4, and an N4 diffusion layer 8 is formed in the other P well 5.
1-, a polysilicon electrode 11 is formed with an insulating film 9 interposed therebetween. Further, 12 is a silicon oxide film.

On the other hand, FIG. 7 is an equivalent circuit diagram of FIG. 6, in which a resistor 13 is formed in the P' diffusion layer 2, and an input terminal 14 is connected to one end of the resistor 13.

In addition, at the PN junction between the P+ diffusion layer 2 and the N type substrate 1,
A diode 15 is constructed, the cathode of which is connected to the power supply VDD via the N+ substrate contact region 3.

A second diode 16 is formed by a PN junction between the P well 4 and the N' diffusion layer 7, and its cathode is connected to the other end of the resistor 13, and its anode is connected to the low potential point VSS via the P+ well contact region 6. It is connected. Further, the N+ diffusion layer 8. A capacitor 17 is constituted by the MOS capacitor of the insulating film 9 and the polycrystalline silicon electrode 11, one end of which is connected to the other end of the resistor 173, and the other end of the capacitor 17 is connected to the low potential point Vss. The capacitor 17 and the resistor 13 constitute a filter circuit, and its output line 18 is connected via an output terminal 20 to a CMO 5 (not shown) formed on another part of the N-type substrate 1.

During normal operation, a signal input from the input terminal 14 is transmitted to 0MO3 via the resistor 13.

At this time, the first. The second diodes 15 and 16 are both reverse biased and non-conducting.

When noise such as electric sweat higher than the power supply voltage VDD is input from the input terminal 14, the first diode 15 is forward biased, and the noise passes through the N-type substrate 1 to the power supply VDD.
bypassed.

Furthermore, when noise or the like with a voltage lower than the low potential VSS is input, the second diode 16 is forward biased,
Noise is bypassed through P-well 4 to low potential point VSS.

(Problem to be Solved by the Invention) However, in the conventional input protection circuit of a semiconductor device as described above, when noise or the like of a voltage higher than the power supply voltage VDD is input from the input terminal 14, the above-described problem occurs. P
+The first layer formed by the PN junction between the diffusion layer 2 and the N-type substrate 1
diode 15 is forward biased, and the noise passes through the N-type substrate 1 and is bypassed to the power supply side VC)D, but at this time, a large number of holes (a small number of carrier) is injected. These injected holes diffuse through the N-type substrate 1, reach other P wells, and cause a change in the charge of the P well, turning a parasitic bipolar transistor or a parasitic thyristor into an ON state, a so-called latch-up. There is a possibility that it may trigger a phenomenon.

In order to prevent this latch-up phenomenon from occurring, P+
The diffusion layer 2 is formed on the N-type substrate 1 at a sufficient distance from the formation site of the semiconductor device such as the CMO 8 (I'1.) to prevent parasitic bipolar transistors etc. from operating. However, taking such a measure has the problem of increasing the chip area.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide an input protection circuit for a semiconductor device that can prevent the latch-up phenomenon and reduce the chip area.

(Means for Solving the Problems) In order to achieve the above problems, the present invention provides a semiconductor substrate 1
- an input protection circuit for a semiconductor device formed on a first conductivity type high concentration diffusion layer formed on a main surface of a first conductivity type semiconductor substrate; and a first conductive layer formed on the side of the junction between the second conductive type semiconductor layer to which the input/output terminal is connected and the first conductive type high concentration diffusion layer within the second conductive type semiconductor layer. By connecting the semiconductor device to the output terminal r- connected to the semiconductor layer of the second conductivity type described in 42, the input protection circuit and the semiconductor device can be connected to one system board 1-. (Function) In the present invention, the semiconductor layer of the first conductivity type is formed within the semiconductor layer of the second conductivity type and on the side of the junction with the high concentration diffusion layer of the first conductivity type. When noise with a voltage higher than the power supply voltage is input, a built-in electric field is generated in the first conductivity type semiconductor layer in a direction that prevents the diffusion of holes (minority carriers). Therefore, the amount of holes injected into the first conductivity type high concentration diffusion layer region is kept low, and the triggering of the latch-up phenomenon is suppressed.

(Example III''I) Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment to which the present invention is applied, and FIG. 2 is an equivalent circuit diagram of FIG. 1.

In FIG. 1, an N medium wave diffusion layer 30 is formed on the side edge of the main surface of the N type substrate 1, and a P type conductor layer 31 is further formed on this N medium wave diffusion layer 30 by selective epitaxial method or the like. It is formed. In this P type car conductor layer 31, N
On the joint surface side with the medium diffusion layer 30, the N in the N medium diffusion layer 30 is
By diffusing type impurities upward, the N-type semiconductor layer 3
1A is formed.

Further, in this example, a resistor 34 is formed of the P-type semiconductor layer 31, one end of which is connected to the input terminal 14 side, and the P-type conductor layer 31 and the N-type semiconductor layer 31A forming the resistor 34 are connected to the input terminal 14 side. A first diode 35 is formed at the PN junction with the first diode 35, and its cathode is connected to the power supply V11D via the N-substrate contact region 3.

It should be noted that the other configurations other than those described above are completely the same as those of the conventional example described above, so the same reference numerals are given and the explanation thereof will be omitted.

By the way, in this embodiment, during normal operation, a signal input from the input terminal 14 is sent to C through the 1° resistor 34.
This will be communicated to MO3. At this time, the first. second diode 3
5 and 16 are both reverse biased and rendered non-conductive.

On the other hand, when noise or the like having a voltage higher than the power supply voltage VDD is input from the input terminal 14, the first diode 35 is forward biased, and the noise passes through the N-type substrate 1 and is bypassed to the power supply side VDD.

By the way, in this case, the P-type conductor layer 31 is used as the emitter and the N
A parasitic lateral PN whose base is the type semiconductor layer 31A and the N medium scattering layer 30, and whose collector is the P well of the internal logic.
A P transistor 40 is formed.

In this case, it is easy to first lower the impurity concentration of the P-type conductor layer 31 forming the emitter of the parasitic PNPI transistor 40. As a result, first, the amount of holes injected into the N-type substrate 1 can be limited.

Furthermore, the P-type conductor layer 31 is located within the N-type semiconductor layer 31A constituting the base region of the parasitic PNPI-transistor 40.
A medium-high concentration region of N exists near the junction, and a built-in electric field is generated in a direction that prevents the diffusion of holes injected from the P-type conductor layer 31 constituting the emitter. Then, the holes injected from the P-type emitter to the base side are recombined by the N0-type high concentration region. For this reason,
Compared to the above conventional example in which the emitter is formed as a single piece and there is no high concentration region in the base region near the emitter-base junction, the movement of holes from the emitter region to the base region is hindered, and the emitter current During this period, the ratio of hole current to 11, that is, the emitter injection efficiency decreases, and the current amplification factor hFE decreases.

Therefore, even if the first diode 35 is forward biased, the collector current of the parasitic lateral PNPI-transistor, that is, the collector current of the parasitic lateral PNPI transistor, is suppressed to a low level, and the triggering of the latch-up phenomenon is suppressed. be done. In addition, this allows the distance between the input protection circuit and the formation site of the semiconductor device such as CMO3 to be shortened.
The input protection circuit and semiconductor devices such as the CMO 8 can be formed on the same substrate H, and the chip area can also be reduced.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a longitudinal sectional view of the second implementation fF1, and FIG. 4 is an equivalent circuit diagram of FIG.

By the way, this second embodiment is different from the first embodiment described in 2.
1 is formed, and in this P-type polycrystalline silicon 41, an N-type polycrystalline silicon 41A is formed at the junction surface flll+ with the N-medium wave diffusion layer 30.

In this f+1, a giantai 44 is formed of the P-type polycrystalline silicon 41, and a first diode (overvoltage bypass diode) is formed at the PN junction between the P-type polycrystalline silicon 41 and the N-type polycrystalline silicon 41A. 45 is formed.

By the way, in this embodiment, a parasitic lateral PNP transistor 50 is formed having the P-type multi-crystalline silicon 41 as the emitter, the N-type multi-crystalline silicon 41A and the N medium scattering layer 30 as the base, and the P-well of the internal logic as the collector. The emitter-base junction is in polycrystalline silicon. on the other hand,
In the vicinity of the emitter-base junction formed of multi-crystalline silicon, there are more recombination centers for holes than in the case of the first embodiment described in Section 2. Therefore, more holes injected from the P-type emitter to the base are recombined than in the first embodiment, and in the parasitic lateral PNPI-transistor 50 formed according to this embodiment, the emitter is further recombined. The movement of holes from the region to the base region is prevented,
The electromagnetic amplification factor also becomes smaller. Therefore, in this embodiment, the latch-up phenomenon is more suppressed than in the first embodiment, and the chip area can also be reduced.

Next, a method of manufacturing the input protection circuit of the semiconductor device shown in the above embodiment will be described.Here, a method of manufacturing the input protection circuit shown in the second embodiment will be explained with reference to FIG.

First, as shown in FIG. 1A, a silicon oxide film 12 is formed on the main surface 1- of the N-type substrate 1. Next, of the silicon oxide film 12 thus formed, the diffusion layer forming portion 30. 3.
7. Remove the silicon oxide film 12 at the portion 6.8.

Thereafter, two P-wells 4.5 are formed on the main surface of the N-type substrate 1, and an N-medium diffusion layer 30° 3, 7.8 and a P-medium diffusion layer 6 are formed in the removed portion of the silicon oxide film 12. will be established. Further, a multi-crystalline silicon electrode 11 is formed by vapor deposition on the N medium scattering layer 8 with an insulating film 9 interposed therebetween.

Next, as shown in FIG. 3(b), a multi-crystalline silicon layer is formed on the N medium scattering layer 30 by selective epitaxial method,
Furthermore, P-type impurities are implanted into the multi-product silicon layer to form P-type polycrystalline silicon 41.

In this way, the P-type polycrystalline silicon 41 is placed on the N medium scattering layer 30.
Once formed, heat treatment is performed in this state to diffuse the N-type impurity in the N-type diffusion layer 30 upward into the P-type multilayer silicon 41, as shown in FIG. N-type polycrystalline silicon 41A is formed in the crystalline silicon 41 on the side of the junction with the N+ diffusion layer 30.

Finally, as shown in the same figure (d), P-type polycrystalline silicon 4
1 is connected to the input terminal 14 and the other side is connected to the output terminal 20 via the output line 18, and the N medium wave dispersion layer 7.1 is connected to the output line 18. The multi-crystalline silicon electrode 11 is connected. Further, the N medium dispersion layer 3 is connected to the power supply side v1)D, and the P medium dispersion layer 6 and the N medium dispersion layer 8 are connected to the low voltage (, 7 points v5s).

In this way, the input protection circuit shown in the second embodiment is manufactured.

In addition, in order to manufacture the input protection circuit shown in the first embodiment, in FIG. layer 31
is formed, followed by heat treatment, whereby N
The N-type impurity in the medium diffusion layer 30 may be three-directionally diffused into the P-type semiconductor 31 to form the N-type semiconductor layer 31A on the side of the junction with the N+ diffusion layer 30.

(Effects of the Invention) As described above, the input protection circuit for a semiconductor device according to the present invention includes the first conductivity type high concentration diffusion debris formed on the main surface of the first conductivity type semiconductor substrate and the first conductivity type high concentration diffusion debris. a second conductivity type semiconductor layer formed on the concentration diffusion layer and to which input/output terminals are connected;
a first conductivity type semiconductor layer formed within the second conductivity type semiconductor layer on the side of the junction with the first conductivity type high concentration diffusion layer, and a semiconductor device is connected to the output terminal. As a result, since the input protection circuit and the semiconductor device are formed on one substrate, it is possible to prevent the occurrence of latch-up phenomenon, reduce the chip area, and obtain the input protection circuit for the semiconductor device. It has the effect of being able to.

[Brief explanation of drawings]

Fig. 1 is a longitudinal cross-sectional view of the first embodiment to which the Kinai nJ1 is applied, Fig. 2 is an equivalent circuit diagram of Fig. 1, Fig. 3 is a longitudinal cross-sectional view of the second embodiment, and Fig. 4. is an equivalent circuit diagram of FIG. 3, FIG. 5 is an explanation of the manufacturing method of the input protection circuit for a semiconductor device according to the second embodiment, FIG. 6 is a vertical cross-sectional view of the conventional example, and FIG.
This is an equivalent garden path map of the figure. 1...N-type substrate 3...N-substrate contact region 4.5...P well 6...P' well contact region 7.8...N" diffusion layer 9...insulating film 11 ...Multi-coupled 1'ii'l silicon electrode 12...Silicon oxide film 14...Input terminal 16...Second diode 18...Output line 20...Output terminal 30...N Medium scattering layer 31...P-type semiconductor layer 31A...N-type semiconductor layer 13.34.44...Resistor 15, 35.45...First diode 40.50
... Parasitic lateral PNP transistor 41 ... P-type polygonal silicon

Claims (1)

[Claims] 1. In an input protection circuit for a semiconductor device formed on a semiconductor substrate, a first conductivity type high concentration diffusion layer formed on a main surface of a first conductivity type semiconductor substrate; a second conductivity type semiconductor layer formed on the second conductivity type semiconductor layer and to which input/output terminals are connected; and a first conductivity type high concentration diffusion layer within the second conductivity type semiconductor layer. a semiconductor layer of a first conductivity type formed on the bonding surface side, and an input protection circuit on one substrate by connecting a semiconductor device to an output terminal connected to the semiconductor layer of a second conductivity type. An input protection circuit for a semiconductor device, characterized in that the semiconductor device is formed with: